Bridging the Gap between Pre-Silicon Verification and Post-Silicon Validation in Networking SoC designs
Dr. Lauro Rizzatti, Verification Consultant
EETimes (8/15/2016 01:55 PM EDT)
De-risking complex networking SoC development is no longer a remote objective; rather, it is available to all design teams today.
Recently, I've been writing a series of articles on the benefits of using hardware emulation for verifying networking system-on-chip (SoC) designs ahead of silicon availability. In this column, I wish to describe a new approach to bridge the gap between the pre-silicon verification and the post-silicon validation of the same networking designs.
In order to set the stage, let's highlight the trends in this highly competitive market segment. The massive adoption of software-driven networking (SDN) architectures has been driven by the upsurge of new markets, such as cloud computing, big datacenters, and mobile. Figure 1 charts the SDN market trend in revenues, which are anticipated to grow by 135% over the next two years.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related Articles
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design