NVM OTP NeoBit in Maxchip (180nm, 160nm, 150nm, 110nm, 90nm, 80nm)
Selecting the right hardware configuration for the signal processing platform
Deepak Shankar
embedded.com (November 21, 2016)
The quality of signal processing systems such as a software defined radio or a communication modem is dependent on the performance of the selected hardware platform. Early design explorations enable the designer to gain insights into implementation challenges, architectural decisions to enhance performance and power, and hardware/software partitioning before Register-Transfer level (RTL) and software are available.
In addition, early design explorations assist architectural design decisions that facilitate planning for current and future requirements. Designers can further extend the design explorations to conduct fault analysis and identify test cases for verification.
This article presents the system level modelling and simulation methodology to architect a signal processing platform for software-defined radios or high-speed communication modems early in the design flow.
E-mail This Article | Printer-Friendly Page |
Related Articles
- A RISC-V ISA Extension For Ultra-Low Power IoT Wireless Signal Processing
- Where Innovation Is Happening in Geolocation. Part 1: Signal Processing
- A framework for the straightforward integration of a cryptography coprocessor in SoC-based applications
- Digital Signal Processing (DSP) Verification
- Selecting the right RTOS scheduling algorithms using system modelling
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)