Embedded processors, cores target broad app range

The Halla design gets its speed primarily from a full custom circuit design and layout with an added boost from the 130-nanometer process technology that Samsung once used for Alpha processors. Halla will deliver 1,480 Dhrystone Mips and sample in the first quarter of 2003.

The company plans to use th e core in future processors aimed at PocketPC handhelds and digital TVs. The core could also be used in 3G handsets, 3-D graphics chips or network processors, Samsung said.

Separately ARM showed its first ARM-11 core in versions with and without a floating-point unit. The synthesizeable core has an eight-stage pipeline and is suitable for implementation at 400 MHz with a power consumption of less than 200 mW.

ARM will deliver the core for the first time in an integrated silicon platform that includes common peripherals such as DRAM and SRAM memory controllers, dual UARTS and a display controller.

"More people are moving to platform-based design because of the number of transistors people are putting into their SoCs [systems-on-chip] and they want to get quickly to market," said Simon Segars, executive vice president of engineering at ARM.

For it's part, Motorola detailed the first superscalar ColdFire processor, the version 5, which extends its software support for the 68000 a rchitecture. The core delivers 610 Mips at 333 MHz in a 130-nanometer process, which Motorola estimates is twice the performance of the current version 4.

ColdFire version 5 uses two execution pipelines based on the single pipeline developed for its predecessor. The device offers optional memory management and floating-point blocks. The core measures 5.2 mm² without caches.

Broadcom's SiByte unit aimed at high-performance networking jobs with its muscular BCM1400. The part could act as a dataplane processor in a network storage switch or on a line card in a router or server. It can handle a variety of networking chores including packet forwarding, TCP/IP termination, ATM segmentation and reassembly or traffic shaping.

The part integrates four SiByte processor cores on a proprietary multiprocessing on-chip bus that can link up to eight chips on a board. The chip sports three interfaces that can flexibly handle either SPI 4.2 for packet transmissions or HyperTransport for PCI or coherent multiprocessing flows between SiByte chips.