English
400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Achieving FPGA Design Performance Quickly
Joe Mallett, Synopsys
EETimes (2/8/2017 11:20 AM EST)
This column highlights the broad steps designers need to complete as they close timing and how tool automation helps to simplify the process.
Today's engineering teams are tasked with delivering FPGA-based products under incredible schedule constraints to market windows. Closing timing constraints is still a challenge for many designers. FPGA design tools are a necessity to help define and apply the correct constraints to a design to quickly close timing and complete the project. This blog highlights the broad steps designers need to complete as they close timing and how tool automation helps to simplify the process.
- Design setup
- Initial timing constraint setup
- Constraints tuning
When starting a new project, designers need to setup the environment and import the IP for the design, which may come from multiple sources. FPGA design tools help automate this process for designers, making it easier and faster while also helping to remove import errors from the process. In addition to the IP import, the tools should automate the constraint import for a given block. These constraints will be shown in the FPGA Design Constraints (FDC) files within the tools, showing the correct syntax for things like clocks, I/O, and clock groups.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Synopsys, Inc. Hot IP
Related Articles
- Achieving FPGA Design Performance Quickly
- Achieving Groundbreaking Performance with a Digital PLL
- Achieving High Performance Non-Volatile Memory Access Through "Execute-In-Place" Feature
- Choosing the right memory for high performance FPGA platforms
- A Method to Quickly Assess the Analog Front-End Performance in Communication SoCs
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- System Verilog Assertions Simplified
- Smart Tracking of SoC Verification Progress Using Synopsys' Hierarchical Verification Plan (HVP)
- Dynamic Memory Allocation and Fragmentation in C and C++
- Synthesis Methodology & Netlist Qualification