SerDes power minimization allows SoC solutions

SerDes power minimization allows SoC solutions
By Khanh Le, EEdesign
October 31, 2002 (8:57 p.m. EST)
URL: http://www.eetimes.com/story/OEG20021031S0048

Editor's note: The following article shows how you can minimize power consumption for SerDes blocks. A related sidebar provides more insight on how the trend towards serial I/O is driving SerDes solutions.

With the advent of deep-submicron processes, system-on-chip (SoC) architects and designers face many challenges. Not the least of these is managing the power budget of multi-million-gate ASICs that are processing gigabit-per-second wire-line data.

The engine for the intensive I/O processing needed to move data on and off chip is a SerDes (serializer/deserializer) macrocell that multiplexes external serial data from Fibre Channel, Serial-ATA, InfiniBand, Gigabit Ethernet and other system-level pipes into parallel data streams suitable for internal ASIC buses. After on-chip processing, the data is serialized and returned to the system in serial streams.

Given its frenetic level of activity, it is not surprising that SerDes often commandeers as much as 75% of the chip's power budget in an application such as a 3.125-Gb/s 64-by-64 crosspoint switch.

Minimizing power consumption of the SerDes block is important primarily because it can mean the difference between a one-chip or multi-chip solution. An accurate power budget is essential to achieve the optimal level of integration. A low estimate that turns out to be incorrect means more time spent in correcting the error with a system repartition and higher cooling costs. In many cases, power consumption of the SerDes core is an important criterion for selecting the ASIC vendor.

SerDes power consumption
Conceptually, a SerDes block has a fairly simple function and requires only about 40,000 transistors to implement (see Figure 1). But its modest transistor count belies its importance in the power equation. Assuming a 0.13-micron CMOS fabrication process and a 3.125-Gb/s data rate, a SerDes block i n a 10-Gigabit Ethernet switch typically consumes about 150 mW per channel. In this scenario, two PLLs consume 15 mW each; the transmitter (TX) and receiver (RX) consume a total of 70 mW; and the I/O consumes 50 mW (50 ohms termination, 1.6 V diff. peak to peak output swing).

With more than 20 players in the market, competition among SerDes vendors for designer mindshare is intense. It is not surprising that specmanship is part of this competition. In order to decode the power consumption specs from competing vendors, however, it's important to understand how operating frequency, design styles, architectural choices, and implementation of testability features affect SerDes power.

Figure 1 - SerDes plays an important role in a 64x64 crossbar switch

A significant portion of the SerDes power budget is directly related to the target application. Operating baud rates for standards such as Fibre Channel, Gigabit Ethernet, InfiniBand can range between 1.0625 and 4.25 Gb/s. Most SerDes include digital logic and analog circuits. The power consumed by digital logic represents between 15 and 20% of the total SerDes power and scales linearly with frequency.

To put this in perspective, the digital logic in the example mentioned earlier will consume about 5 mW at 1 Gb/s and 25 mW at 4.25 Gb/s. Analog circuits contribute more milliwatts to the total but do not scale linearly. The same receiver that consumes 25 mW at 1 GHz, for example, consumes 35 mW at 4.25 GHz. In general, frequency-dependent circuits consume about 50 % of total SerDes power so using standard CMOS gates wherever possible will lead to lower power .

CML or CMOS?
Intelligent design choices are the most effective means of controlling this part of the budget. A SerDes implementation using extensively CML (Current Mode Logic) is bound to consume more power than an equivalent one with more standard CMOS circuitries.

CML is typically chosen over standard CMOS for its superior noise immunity. Noise immunity is critically important at high data rates and with the low voltage swings encountered by SerDes blocks. Noise is not problematic for most of the digital logic or for many high-speed analog circuits within the transmitter and receiver. So, carefully choosing low-power CMOS where noise does not adversely affect functionality is an important design decision . Changing the circuit technique from CML to CMOS in those areas can reduce power by as much as 50% .

Another application-specific component of the SerDes power budget is the combination of termination resistance and voltage swings specified by the various standards such as Gigabit Ethernet and Fibre Channel. Table 1 shows the termination resistor values, output voltage swings, and typical I/O power for nine high-speed serial interconnect standards. I/O power consumption varies between the high of 48.4 mW for 4.25 Gb/s Fibre Channel and the low of 12.8 mW for 1.5 Gb/s Serial ATA. The variation is impo rtant because vendors find it convenient to quote SerDes nominal power consumption values and for applications with the lowest power to win designs.

At the end of the day, designers and SoC architects must ferret out the power figures for their specific application and be sure all components are included in the budget.

Table 1 - How I/O power varies with termination resistance and voltage swings

Clock design
Clock recovery on the receiver side of the SerDes block, and clock generation on the transmission side, involve PLL (Phase Lock Loop) or DLL (Delay Lock Loop) circuits. This is an area in which clever design can make a difference in power consumption. But care must be taken with the trade off between power and other aspects of the design.

Typically, SerDes blocks are designed with one PLL for each transmitter and one for each receiver. Each PLL consumes about 15 mW. A fairly common power-saving technique is t o use just one PLL for both functions. However, no net power saving is achieved since a subsequent DLL is required in the receiver to align the clock phase to the incoming data. Having the transmitter and receiver operate asynchronously is an important feature in switch and host adapter applications, for example. By sharing a PLL between multiple transmitters but still having a dedicated PLL for the receiver clock recovery, one can preserve most of the flexibility.

Another frequently chosen design option is to replace the analog PLLs with digital PLL or DLL (Delay Lock Loop) circuits that consume less power but introduce other trade offs.

No hidden charges
When calculating a power budget, SoC architects and designers must be sure that all SerDes functions are counted. One tactic SerDes vendors use to reduce the apparent power requirement is to assume that some blocks are optional.

Much to the chagrin of designers who do not look closely at vendor specs, I/O power is sometimes not qu oted as part of the SerDes block. Especially important for good signal integrity are the on chip termination resistors. The power dissipated through them is real and must be included in the chip's power budget. As a matter of practicality most designers would choose to include I/O power in the SerDes block.

Omitting test circuitry is another fairly common way to reduce apparent power dissipation. BIST (built-in self test) circuits typically employ a loop-back mode technique to exercise the critical circuitry in the transmitter and receiver in test mode. Boundary scan increases test coverage by providing accessibility and control of critical circuit. These additional test circuitries load critical nets inside the SerDes during normal operation, however, and increase power accordingly. But eliminating SerDes test circuitry is usually not an option since it has the obvious downside of reducing the overall test coverage of the ASIC.

LSI Logic's GigaBlaze SerDes core implemented in our 0.13-micron G flx process provides an example of low-power design techniques. The GigaBlaze specs are quoted at typical (nominal process, 25o C, and nominal supply voltage) and at the worst-case PVT conditions (fast and slow process, 0º-125ºC and ±5% supply voltage), with the specified output voltage swings for supported serial interconnect standards to ease the ASIC designer's power budget calculations. By using CML only in those circuits where it is needed, sharing one PLL between four transmitters, and implementing other low-power design techniques, the GigaBlaze core consumes in nominal conditions less than 90mW per channel in a Serial-ATA application.

Conclusion
From a designer's perspective, the key to a successful ASIC starts with ensuring that the power budget reflects the intended application, the actual specifications in the standard - especially the output termination and amplitude -- and includes contribution from all of the required functions.

To arrive at a realistic power budget, desig ners should ask themselves these two questions: Is the vendor quoting power dissipation based on the actual specifications in the standard? Is typical or maximum power consumption being quoted?

In addition, the power consumption of I/O and test circuits is often left out in spec sheets. By taking care to make apples-to-apples comparisons, designers can get an accurate power budget and make informed decisions about chip partitioning, package selection and cooling requirements .

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