The case for integrating FPGA fabrics with CPU architectures
By Alok Sanghavi, Achronix Semiconductor
Physics restricts how much further process geometry shrinkage can take us in terms of boosting processor throughput.
As this happens, designers are debating how they can approach designs in such a way that they’re not relying on packing yet-more transistors onto a chip to achieve speed increases. One of the biggest innovations in this industry is going to come from a fundamental reapplication of a technology that has been known and understood for some time; enter the humble FPGA.
FPGAs started life as discrete devices in 1984. At this time Xilinx and Actel started to introduce products primarily used in low-volume industrial applications and prototyping as useful ‘band aid’ to patch holes in system logic. Altera Lucent and Agere drove FPGAs into networking and telco applications. Subsequent process shrinkage, reduction in mask costs, and the integration of SRAM blocks, large MACs, sophisticated configurable I/O and banks of SerDes marked a growth in FPGAs from 1995. Over the last 10 years FPGAs have continued to proliferate and prices have fallen to the point that FPGAs are adding significant value even to high-volume applications in functions previously associated only with DSPs, GPUs, and MCUs.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
- CPU Soft IP for FPGAs Delivers HDL Optimization and Supply Chain Integrity
- Using FPGAs in Mobile Heterogeneous Computing Architectures
- How FPGAs, multicore CPUs, and graphical programming are changing embedded design
- Optimize data flow video apps by tightly coupling ARM-based CPUs to FPGA fabrics
- CPUs in FPGAs: many faces to a trend
New Articles
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
Most Popular
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects