Overcoming Timing Closure Issues in Wide Interface DDR, HBM and ONFI Subsystems

By Brian Gardner, True Circuits

ABSTRACT:

In wide chip interfaces like DDR, HBM and ONFI, it can be challenging to synthesize and connect high-frequency controllers to the PHY hard macros. Clock trees can be expansive, pushing tools to their limits, and often multiple clock domains are needed. Jitter can also be an issue on long paths. In this presentation Brian will show how True Circuits PLL and DLL IP is being used by multiple customers to build ONFI and HBM subsystems in advanced TSMC process nodes, and discuss the tradeoffs and timing budget concerns among different timing architectures. In addition, he will explain how source-synchronous signaling is used in our DDR PHY to ease timing closure, and to allow the memory controller to be synthesized for high-frequency operation, which reduces its size and lowers its latency. By using a soft IP "shim" between the memory controller and PHY, the memory controller only needs a single localized clock tree, reducing mismatch and jitter. The long routes between the soft shim and the PHY hard macros are source-synchronous, so data/strobe groups need only be roughly matched, something easily accomplished by place and route tools.

AUTHOR:

Brian Gardner is TCI's V.P. of Business Development. He is a long time semiconductor industry veteran, and has spent the last 11 years in the semiconductor IP market. He has held senior positions in general management, marketing and business development at Denali, Cadence, QLogic and Motorola. Brian is well known for his knowledge and experience in IP subsystems, particularly DDR and ONFI.

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