The Secret to Building IP at the Cutting Edge
By John Maneatis, True Circuits
At 7nm and beyond, the cost and time to develop IP is very high. To gain a suitable return, it's critical to have an efficient design methodology that produces a portfolio of attractive solutions in many process variants, metal stacks, Vt selections, and even completely different foundries. TCI employs a range of fascinating techniques, from building robust circuits, to using proprietary extensions of CAD tools to creating designs and deliverables from one, universal database. In this presentation John will explain the engineering behind a highly automated CAD flow that enables TCI to maximize IP consistency, quality and reuse.

AUTHOR:
John Maneatis is TCI's co-founder, President, and Chief Technologist. He holds a B.S. degree in Electrical Engineering and Computer Science from U.C. Berkeley, and M.S. and Ph.D. degrees in Electrical Engineering from Stanford University. John has almost 30 years of experience in analog and digital circuit design and is world renowned for his work in the area of Phase-Locked Loop design. He has given multiple authoritative presentations at the IEEE ISSCC and regularly presents at industry trade shows on topics of analog design, circuit simulation and CAD development.
If you wish to download a copy of this white paper, click here
|
True Circuits, Inc. Hot IP
Related Articles
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- Menta eFPGA IP for Edge AI
- The benefit of non-volatile memory (NVM) for edge AI
- Handling the Challenges of Building HPC Systems We Need
- How Efinix is Conquering the Hurdle of Hardware Acceleration for Devices at the Edge
New Articles
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
Most Popular
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- UPF Constraint coding for SoC - A Case Study
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |