NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
SoC Functional verification flow
Dilip Prajapati, eInfochips
December 14, 2017
This paper presents SoC- (System on Chip) level functional verification flow. It also describes ways to speed up the process.
To ensure successful tapeout of SoCs, here are the steps of a standard SoC-level Functional Verification flow:
1. SoC Level/Top Level view (Feature Extractions)
During SoC verification, you must view the design at the top level and extract its SoC level functionality/features during specification study phase for its verification. At this stage, a thorough understanding of SoC functionality and its architecture is required because misunderstanding of the specification can become the leading cause of bugs, and due to this you may waste unnecessary time on issues which are not real RTL problems.
2. SoC Level Verification Plan
- Define a Clear Line Between SoC and IP
During the development of the SoC level verification plan, you have to clearly define/identify the functionalities, which needs to be verified at the SoC level and at the sub-block or sub-IP or sub-cluster level. The same verification needs to be confirmed during the review with the respective verification team to avoid any last-minute surprises.
- Identify Reusability Components
You must also check which block or sub-block level verification components/environment and scenarios can be reused at the SoC level with a reusability point of view to reduce its new development time at SoC level.
- Verify Interconnections
At SoC level, you mainly have to focus on the top level functionalities of the SoC along with verifying whether the intercommunication between the sub-blocks occur properly or not. You have to also verify the connection of the sub-modules with the top. - Keep Placeholders for Updates
Sometimes, all the features of the SoC are not defined at the initial phase of the SoC verification planning. For those types of features, you need to update the verification plan at a later stage. Hence, during verification plan development, you can put placeholders or FIXME for the same to update the features when the need arises later on.
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