Keynoter sees asynchronous future for digital designs

Keynoter sees asynchronous future for digital designs
By Richard Goering, EE Times
December 4, 2002 (2:09 p.m. EST)
URL: http://www.eetimes.com/story/OEG20021204S0018

MONTEREY, Calif. — A shift to asynchronous design styles is "inevitable" for digital computing systems, according to Ivan Sutherland, vice president and fellow at Sun Microsystems Laboratories. Sutherland brought that message this week to what may be an unlikely audience-the Tau workshop on timing analysis, which focuses on EDA tools and methodologies for synchronous digital systems.

In his keynote speech, "Computers Without Clocks," Sutherland argued that asynchronous design styles will become important for addressing performance and power concerns, as well as allowing modular upgrades to large chips. He acknowledged, though, that design tools and methodologies are lacking, and that real-world examples of asynchronous logic chips are few.

"I believe asynchronous design is going to creep into our systems," Sutherland said. "The synchronous paradigm has so many problems that we've got to look at what our alternatives are."

But that does n't mean there will be a wholesale shift to asynchronous design, he said. There are many possible approaches, such as CPUs that are synchronous internally yet communicate asynchronously with memory, he noted.

Sutherland said there are some good things about fixed-period clocks, such as the "regularity" of being able to predict clock intervals. But there's a lot of bad news, too, he said. Because it takes a lot of power to get a time signal delivered throughout the chip, clock skew becomes a problem. The speed of light becomes a limitation in GHz chips, and "uncertain component properties," such as process variations, will make it important to deal with component timing independently, he said.

Perhaps the worst news for designers, Sutherland said, is that every communication path must meet the requirements of the external clock-making it difficult to focus on the 10 percent of paths that do 90 percent of the work. Further, there's the "modularity" argument.

"You can't just take a little piece of t he system and improve it," Sutherland said. "The whole system needs to be upgraded together, and I think this hurts a great deal. I look to the day when we can upgrade systems like we upgrade subroutines."

Sutherland also listed a number of arguments for asynchronous design. They support faster time-to-market, he said, because designers don't have to be so careful about circuit timing. They reduce power because clock gating is "free," and have fewer problems with electromagnetic emissions. Finally, they're faster-in Sun's experiments, he said, asynchronous chips often run twice as fast as synchronous chips.

One hurdle to asynchronous design is state explosion, given that there are billions of possible states a system could be in. Sun has addressed that problem with pipelined systems, Sutherland said. He also said that EDA tools are lacking. "The level of effort that has gone into tools for asynchronous design is not anything like the effort for synchronous design, because there aren't as many people involved," he said.

The crux of an asynchronous design methodology, Sutherland said, is to "focus on sequence rather than time." One promising approach is "source clocking," which sends timing signals to a given destination along with data, and also accepts acknowledgement signals coming back.

"Asynchronicity is a matter of attitude," Sutherland said. "Do I want someone else to provide the time, or do I deal with time on a case by case basis?"

Sutherland said that we don't know if a 100-million transistor asynchronous computing chip would work, because no one has built one. In response to an audience question, he said the largest asynchronous chip built at his laboratory is around 250,000 transistors. "These are toys, not very complex, but the idea is to teach us about circuits," he said.