Analog IP re-use: concerns for "digitally-oriented" SoC designers

For system designers, the re-use of existing analog blocks is critical to meet time-to-market pressures for the product. System integrators have the option of turning to re-use analog IP from previous SoC designs or purchasing analog IP from external vendors, as part of a foundry offering or from fabless IP vendors.

For example, as RF-CMOS process technologies advance with improved passives and scaled FET devices, the option of integrating the RF front-end becomes more attractive. However, the placement of a large RF block is not obvious and can lead to the design being late and not working first time. Footprint is one of many parameters, the SoC designer needs to consider.

Other parameters that force design issues in IP re-use include:

-Process scaling/migration (0.25 µm to 0.18 µm). This leads to voltage scaling, interconnect pitch scaling, higher integration on the IC, and device performance changes.

-Process change (from foundry A to foundry B). Even at any single process technology node, it is rare to see two foundries with the exactly same process — the same GDSII leads to two slightly different designs. Notably, even in the same foundry, advanced process technologies change frequently as they mature, leading to possible impacts to the analog design.

-Design specification change. For instance, using a PLL that is needed to work at 400MHz instead of the original 250MHz. It is very rare for analog IP to be re-used with exactly the same design performance requirements.

-Integration onto different chips. A data converter integrated in a wireless design with a 100MHz digital clock frequency in the micro-controller, may perform differently when integrated onto a wired communications IC with a 800MHz clock, due to a different noise environment and footprint constraints.

-Different CAD environments. Different spice simulation tools have different device model implementations leading to possible differences in simulation results. This problem is also significantly true for interconnect extraction and generally any parasitic extraction tools.

There are several issues derived from these changes:

-Voltage scaling, say from 2.5V to 1.8V can lead to headroom and signal-to-noise ratio problems. The noise floor becomes more a problem to deal with, and signal propagation times are affected.

-Device scaling leads to 1/f noise being more of a problem for the designer, especially in CMOS technologies. Wireless receivers and PLL's are often affected.

-As process technologies scale, the CMOS designs require lower passive values, for example, the inductor requirements in PLL's fall as the frequency of operation rises. The tolerance on passives is typically absolute and therefore does not scale down as the passive devices become smaller, causing higher percentage effects on design performance as the absolute values lower.

-Testbench reuse, where an analog IP may operat e the same under nominal conditions, but there is a need for the simulations to include the same parameter changes such as temperature sweep, to ensure that the IP works to specification. It is easy for an integrator to miss a subtle performance point in an analog IP, due to inexperience with analog testing.

-Layout and footprint may present problems for IP. It is common for analog IP to have the wrong aspect ratio and/or footprint size, leading for the need to rework the GDSII. This can lead to a major rework of the design itself as any change may impact the circuit's performance.

-Interconnect pitch scaling is an inherent part of process scaling. The side-effect is that the parasitics of the interconnect, and the resulting signal integrity effects, change between technologies. When integrating analog IP, this can be a critical problem. One example: the performance of an LNA can be extremely sensitive to the RLC parasitics on the input interconnect.

-Chip noise issues may vary significantly. The clock frequency typically generates a predictable substrate noise pattern in the substrate. A different clock frequency may lead to different noise coupling issues on the analog IP. There are many different paths for this problem to show itself, and experience is a key part to understanding how to model and mitigate these issues.

-The analog IP may be poorly "packaged" for the integrator. This means that the views, abstracts, and documentation of the IP may not be adequate for the integrator to successfully integrate the analog IP. One of VSIA's core missions is to provide guidance for this topic — in the analog, digital domains, and with signal integrity issues.

Such issues can force analog IP designers to redesign the schematic and layout views to meet different budgeting of timing; dynamic range; loading; gain; power; and parasitic noise concerns. As these specifications vary, the synchronization between sub-blocks needs to be often redesigned and then re-ve rified. The SoC integrator needs to factor in such re-design early in the project.

Analog IP re-use issues are difficult and complex. Much thought and preparation is needed for the integration to be successful. For instance, a well-designed and verified analog and parasitic-aware CAD environment is very important. Another key requirement is thorough "packaging" of the IP for the integrator. And, although not always possible, it is invaluable to have an experienced analog engineer working with the "digital" SoC team to ensure that the IP is integrated successfully.