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400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Verify Smarter, Not Harder
By Mark Olen, Mentor, a Siemens Business
EETimes (April 1, 2019)
Process technology and verification enjoy a circular and mutually beneficial symbiotic relationship. Improvements in functional verification tools make technology adoption economically viable, and technology advances spawn more complex designs, which demand an increase in sophisticated verification.
Process technology and verification enjoy a circular and mutually beneficial symbiotic relationship. Improvements in functional verification tools make technology adoption economically viable, and technology advances spawn more complex designs, which demand an increase in sophisticated verification.
To keep up with the rapid pace of innovation and rising design and verification complexity, engineering teams need to verify smarter, not harder. New and reimagined technologies and methodologies — including portable stimulus, coverage, and power-aware verification — give them the tools to do so.
Functional verification is the science of validating a representation of a particular chip design targeted for a given technology. This validation must be of a sufficient accuracy and rigor to make the end product economically viable. It can do so by maximizing the likelihood of high-quality, first-silicon working in the end application with the greatest possible number of scenario variants.
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