SoC Interconnect: Don't DIY!
By Kurt Shuler, Arteris IP
EETimes (June 12, 2019)
With so many acquisitions in the interconnect IP market, you might be forgiven for thinking DIY interconnect is a good idea.
FlexNoC 5 Network-on-Chip (NoC) FlexNoC 5 Option For Scalability and Performance Critical Systems | Related |
There’s been a lot of action in the interconnect IP market over the past year – most notably the acquisition of NetSpeed by Intel and Sonics by Facebook. What’s happening? Why are companies seeing the critical importance of interconnect IPs now? Is interconnect a key factor in system-on-chip (SoC) delivery productivity for multi-SoC project corporations? Are these acquisitions a way around the fact that interconnect development is lengthy, costly, and difficult?
The recent market consolidation might have some companies considering whether this is a do-it-yourself (DIY) project that your company should consider taking on. Whether it’s a simple crossbar switch or a full-function network-on-chip (NoC) architecture for advanced SoCs, all that’s needed are the right people with the right knowledge and a big budget; eventually, it could happen. But the question isn’t can you do it? It’s should you do it?
E-mail This Article | Printer-Friendly Page |
|
Arteris Hot IP
Related Articles
- Easing Heterogeneous Cache Coherent SoC Design using Arteris' Ncore Interconnect
- Don't over-constrain in formal property verification (FPV) flows
- Supply Noise Induced Jitter - Don't Let it Kill your Chip
- Graphics processing: When DIY just doesn't make sense
- Don't Let Metastability Cause Problems in Your FPGA-Based Design
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)