Taking on the 130nm node and beyond

Today, more demanding applications are challenging the ASIC technologies. Our 130nm technology is up to the task, however, harnessing this power is impeded by constraints inherent to the technology node.

For example, capacitive coupling creates signal integrity problems. Gate oxide stress increases with coupled noise. False switching opportunities are exacerbated by tight metal pitches, highly resistive wires and fast edge rates. Delay modulation from coupled noise has been evident largely as second order for the past two generations but is now first order.

Power distribution also presents issues. Competition for available metal is stiff with high gate and signal density. Higher resistance from thinner metals and deeper metal stack-ups along with increasing power density at lower voltages demands more robust power distribution systems.

Meanwhile, gate, memory and I/O counts introduce tool capacity and run time issues and significant disk and CPU resource demands. Data management and coherence in a hierarchical methodology present logistical problems. The workload of executing multi-million gate designs over manufacturing and application space burdens the design team and design system.

Addressing all of these challenges requires a robust design flow, a good library and a capable design team.

Tools and flows that accommodate hierarchical designs are needed at this node. State-of-the-art floorplanning and place and route tools are used to partition and build the design while concurrently pushing timing closure . Solutions are scripted for re-execution to ensure that iteration is not hampered by repeatedly solving the same problems. Proprietary design tools supplement those available from third party vendors in the evaluation of signal integrity and IR drop. Power and signal electromigration are evaluated using proprietary flows.

TI's library offerings satisfy a variety of applications. For example, we offer a peak performance library and technology; a high density and low leakage library and technology; and a hybrid solution coupling the high density library image with the high performance library's memory, I/O and technology to provide a good compromise for customers who need good performance but are more silicon area or price sensitive.

The company's ASIC operation has evolved to more closely resemble a high-performance custom IC design house. Broadly experienced design teams skilled in all areas of the IC design process allow us to tackle our customer's high performance design needs.

Mod ern ASIC design demands a staffing profile geared towards concurrent design. Depending on the difficulty of the timing closure loop and subchip size, a single designer can handle 2 to 3 subchips. The top level requires one or two designers depending on the complexity of the clock and power distribution problem and on the number of hard macros. Frequent evaluation of toplevel and subchip interactions is needed. Customer feedback milestones must comprehend subchip and toplevel design cycles.

High-performance designs presented to TI at the 130nm node often require flip-chip solutions. Flip-chip can make power distribution easier. Coupled with hierarchical design, it complicates the evaluation of the power grid. The level of hierarchy containing the bumps and top level metal affects power distribution modeling and routing resource utilization.

Subchip partitioning is based on a number of factors — size, gate count, memory count, run-time for place and route, the number of independent clock d omains in the design, and reuse opportunities.

Long-distance routing creates the need for frequent buffering. This drives decisions such as whether to allow over-routing or define routing channels. Edge rates are degraded, affecting timing into the subchip which must be budgeted and validated. It is important to ensure that contracted area, timing and routing budgets are maintained.

Multidimensional optimization

TI's tools and flow allow us to tackle the problem presented to the designer--the implementation of multi-million gate designs optimized for delay--in mission mode, while at the same time avoiding hold time violations and ensuring at-speed operation under all operating conditions. Noise events must not create reliability or functional failures.

Concurrent optimization of max and min delays is required to ensure convergence. Adding noise awareness to the optimization provides a significant improvement. Further enhancement in the complexity of the optimization aids convergence at the expense of design cycle time.

Validation steps can uncover issues like crosstalk violations that will require design rework, so tools which allow incremental updates are needed.

Edge-rate degradation on clocks due to large loads and RC delays cause deep clock buffering with accompanying jitter increase. Clock insertion delay engineering to capture cycle time improvement creates the need for automated hold-time buffering. The routing resources consumed by high speed clocks are large.

Fast clock edge rates make the clock routes very significant noise aggressors. Options are available to compensate or protect against these effects such as wire width and space engineering or shielding. The interaction between these solutions and routing and power resources demand intelligent routing tools.

Chips designed in 130nm technology are highly integrated, containing many synchronous and asynchronous clock domains. Managing a large number of clock distributions with intra-domain constraints is a challenge handled using clock tree synthesis and analysis tools.

High-speed SERDES include complex clocking requirements. TI has succeeding in addressing this challenge. Attendant complexities in the implementation require a thorough understanding of the routing, power, placement, and clocking rules. Close interaction between ASIC implementation and SERDES design teams ensures success.

The generation of highly structured switched core architectures has also been addressed. These solutions leverage regular logic structures to generate regular placement and routing solutions for switch applications. Advice on the RTL coding styles that best optimize this solution is available.

Tightening the final implementation loop

Handoffs between physical design and layout are being eliminated or minimized to close designs quickly and reliably. The high degree of interaction between design and verification steps requires a tight loop. T he design team manages the entire design flow from netlist to tape-out to improve the design cycle. Close interaction with our product engineering and manufacturing teams ensures reliable prototype and production delivery schedules.

We have successfully tackled the challenge of designing large high performance ASICs at the 130nm node. The current and future success of ASIC customers is dependent on suppliers who provide high performance design capability in a highly productive environment, and we have demonstrated that we do.

We are currently manufacturing and designing at the 95nm node and applying the same skills, experience and innovative thinking to address the challenges.