Speed demands accurate models

Today's data rates of backplane serial links are in the 1- to 3.125-Gbit/second range. To increase capacity within existing form factors, system developers want to extend electrical backplanes to 5- to 10-Gbit/s data rates. Silicon, connector and pc-board vendors have made progress to make those higher data rates possible, and system vendors are already evaluating the ultrahigh-speed serial links for implementation in their next-generation products.

Backplanes provide the connection between line cards and switch-fabric cards. Models help predict the electrical metrics such as loss, reflection, crosstalk and skew that affe ct the system response. System vendors need accurate and efficient models for both the active and passive components of the system for making design trade-off studies, system budgeting and margin studies, and component parameter sensitivity analysis. Silicon vendors need passive channel models to design proper on-chip circuits for implementing techniques like equalization and crosstalk cancellation. In addition, modeling all known deterministic effects of the channel eliminates signal integrity issues in production.

To develop a proper channel model, models for the connectors, packages, pc board traces and vias are needed. Either a vector network analyzer (VNA) or a time-domain reflectometer/time-domain transmission (TDR/TDT) instrument can measure and verify loss, reflection, crosstalk and skew. The models are in the form of S-parameters, HSpice-compatible W-element transmission lines or lumped elements and can be used in simulators like HSpice from Synopsys Inc. or Advanced Design System (ADS) from Agilent Technologies.

As the performance requirements increase, the foremost criterion for selecting a connector is its signal integrity performance. Other attributes of the connector, such as its mechanical robustness and reliability, ease of routing and connector density, must also be considered. Surface- or pressure-mount backplane connectors are perceived to offer electrical advantages over traditional press-fit connectors, which require large plated-through-hole (PTH) vias. Surface- or pressure-mount connectors may offer less mechanical robustness and reliability. Those types of attachments are not field-repairable, must overcome a large thermal mass for reflow of the surface-mount connector and may have an unachievable flatness specification for the backplane. Backplane connectors must also have high signal density to achieve bandwidth requirements without sacrificing routing. This is a delicate balance with conflicting requirements of connector density, minimum card pitch, routing density and signal integrity performance.

With today's multigigabit-system data rates, OEMs require connector vendors to supply highly accurate Spice models of the connector and of the attachment to the pc board itself, whether it is press-fit or surface/pressure-mount. The connector companies generate lumped-element Spice models using 2-D or 3-D tools and verify the models with TDR/TDT and/or VNA measurements. Connector vendors provide test boards with through-reflect-line (TRL) calibration structures that let customers make their own measurements to verify the provided Spice models or to develop higher-order models that take into account the frequency-dependent effects. Most connector companies supply Spice models and evaluation test vehicles under a nondisclosure agreement.

Package modeling must address three distinct regions. First is the chip-to-package interface, which is commonly wire bond or flip-chip. That interface can be modeled with a 3-D modeling tool like High-Frequency Structure Simulator (HFSS) from Ansoft Corp. The inputs to the model are the signal wire bonds/bumps and the surrounding ground as well as power wire bonds/bumps, which can be considered as ground for modeling purposes. The model outputs are the S-parameters for the signal nets considered. Depending on the length of the bond wires, the S-parameters may be fit to one or two W-element transmission lines. For very short wire bonds and bumps, lumped elements may be used for the model.

The second interface to model is the package-to-board interface, which should include the package ball, pad and via and board pad. Again, a 3-D modeling tool can be used. The modeled S-parameters of the signal lines should include the effects of the surrounding power and ground balls and pads. The third region covers the package traces, either microstrip or strip-line transmission lines. At high frequencies, where skin effect dominates, they can be effectively modeled by 2-D tools, with W-element models derived from the resistance, inductanc e, conductance and capacitance matrices. The corner-case models for the traces can also be developed from the 2-D tools. Package model correlation is complex.

Calibrated VNA probes may be placed directly on the ball landing pads and the bump landing pads or bond fingers of the package. But that technique does not include the balls and bumps or wire bonds of the package, but the model can be developed without the balls and bumps/wire bonds and verified in that manner. Elaborate TRL calibration structures are needed to include the effects of balls and wire bonds/bumps.

The pc board traces in the backplane, line card and switch card need to be modeled and are the largest contributors of loss. Typically, the differential traces are either edge-coupled or broadside-coupled strip lines. The traces do not change layers in a component except in the line card or in the switch card in the case of ac-coupled links to facilitate the placement of a series capacitor. In the ac-coupled case, the capacitor pads and the associated vias also need to be modeled. The capacitor's equivalent series inductance (ESL) and resistance (ESR) can be added in series to the capacitance. The traces can be modeled using 2-D tools at high frequencies where the contribution to the inductance matrix from the internal inductance of the conductors is negligible.

Accurate modeling not only requires accurate tools but also the correct material parameters like relative dielectric constant, dielectric loss tangent, effective conductor conductivity and true physical dimensions of the trace width and thickness, and dielectric heights. That makes correlation even more important for trace modeling.

The models can be correlated to measured S-parameters. TRL calibration procedures can remove the launch parasitics and extract the true S-parameters of the trace. The true physical dimensions of the pc board can be obtained by cross-sectioning the board. If the correct material parameters of the board are not known, then the mat erial parameters can be adjusted to fit the modeled S-parameters to the measured S-parameters. Once the models are correlated, the models for pc board corner cases can also be obtained.

All the vias in the signal path across the backplane, line card and switch card need to be modeled. These include the pc board vias at the package and the vias at the ac-coupling capacitor in addition to the connector PTH vias on the backplane and the line card/switch card. The 3-D modeling tools can be used to model the vias by entering via dimensions, pc board cross-section and the recommended anti-pads at the power and ground planes. Ports exist only on the top and bottom layers and there are no trace hookups along the via. The modeled S-parameters can be fitted to a W-element transmission line. The modeled S-parameters can then be verified with measured S-parameters obtained by placing calibrated VNA probes directly on the top and bottom pads of the signal and ground vias.

Using 2-D tools

A nother modeling technique for the vias is to use 2-D tools to model the capacitance and inductance matrices. When the via model is implemented in channel simulations, the via transmission line can be broken into two sections, one representing the signal-through portion and the other representing the stub portion. Once the PTH via model is known, the counter-bored via model can also be implemented in the channel simulations like the PTH via, except with a shorter stub length.

The power delivery network is critical in controlling jitter and noise induced onto signal lines. Accurate models of the power and ground planes, and decoupling and bypassing caps on the boards and packages with their ESL and ESR included, as well as the associated power and ground vias, balls and bumps/wire bonds are essential for simulation of the power delivery network. Simulations can be run to predict the dc drop, effectiveness of bypassing and decoupling and ac noise on the power and ground network for a given current prof ile of the chip. Measurements can be done on the power and ground network to verify the models. Modeling on-chip parasitics (electrostatic discharge and device capacitances and termination resistances) is another critical area influenced by silicon design.

Once the passive-component models are developed, the channel model is put together. Silicon test chips can be designed that inject a controlled rise time step into the channel on the transmit side and then measure and output the step response. The channel transfer function, with the on-chip effects included, can be simulated and compared with the Fourier transform of the measured in situ step response. The measured and modeled transfer functions of a representative backplane channel are plotted with very good agreement.

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