How to Verify Complex RISC-V-based Designs

By Zibi Zalewski, Aldec
EETimes (May 28, 2020)

As RISC-V processor development matures and the core’s usage in SoCs and microcontrollers grows, engineering teams face new verification challenges related not to the RISC-V core itself but rather to the system based on or around it. Understandably, verification is just as complex and time consuming as it is for, say, an Arm processor-based project.

To date, industry verification efforts have focused on ISA compliance in order to standardize the RISC-V core. Now, the question appears to be, How do we handle verification as the system grows?

Clearly, the challenge scales with multiple cores and the addition of off-the-shelf peripherals and custom hardware modules

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