Solving a problem like reuse

By Sowmyan Rajagopalan, Founder and CTO, Thalia Design Automation

Analog IP reuse often equates to tough choices for semiconductor companies.

To invest the time and resources in reusing an analog IP requires a judgement call on the potential returns from the market and the time it takes to get the IP to that market to generate revenue is key – if a competitor project hits the market first, then the potential returns are greatly diminished. There is also a need to understand the differences in process technologies and the impact those differences have on the efficient reuse of analog IPs. All this means that the demands on resources and time are high.

Decisions, decisions

A typical decision fork faced by many semiconductor companies is whether to design new IPs, or if they should instead build a portfolio of analog IPs. Given the opportunity cost, availability of resources, time and resources needed for each option means that doing both is a difficult option.

Both have their advantages; designing new IPs allows companies to branch out and address new sectors or markets. New IPs often demand higher revenues and engages in-house designers as the work, by its nature, is more innovative and challenging. On the other hand, building a portfolio of analog IPs allows companies to expand in an existing market, bringing stabilisation and strengthening revenues from existing product sectors.

But why should semiconductor companies have to choose when there’s a third option?

Have your cake and eat it

It is difficult for a company to drive both options internally – not least because there’s a paucity of good analog designers in the market, and the opportunity cost is simply too high. However, the good news is that firms like Thalia have the specialist expertise and toolsets required build a portfolio of analog IP, saving time and investment while in-house designers focus on new IP design.

Addressing the complexity

Analog circuit design is a complex process, impacted by a number of factors ranging from device performance, process technology characteristics, market needs and the design methodology deployed within a company. This essentially makes reusing IP almost a complete redesign. Even a Bandgap is less of a tweak and more like a redesign. Added to this, limited usable solutions in a given marketplace and, as previously mentioned, a lack of circuit designers which exacerbates the problem and begs the question: is efficient analog IP reuse a myth or a dream?

Waking up

Solving the issues of complexity requires the use of new methods and, most importantly, targeted automation. Total automation is a myth – it’s simply too complex to achieve without expert human input. To illustrate this, the following is a case study of an IP reuse project undertaken by Thalia using our targeted automation platform.

Amplifying the benefits

Our case study is that of an audio amplifier – a whisper trigger amplifier – that was migrated from 40nm to 22nm technology. The amplifier is a four-stage amplifier with comparators at the end connecting to a DSP. The key objective was to achieve a power saving within SOC, largely achieved by putting the ADC to sleep, and activating it only when there is a voice detected.

To achieve this, tasks around the circuit and process technology differences had to be defined, which highlights the first challenges design teams face when migrating IPs. By deploying our IP reuse platform, we could leverage the targeted automation functionality to identify the root cause of the design issues and create a solution that incorporated the changes to topology demanded by the target technology.

Technology analyzer – identifying the root cause when circuits fail

A large part of the effort involved with migrating an IP from one technology to another is involved with qualifying the IP in the target technology; if a block doesn’t meet the requirements of the target technology, it won’t function. With this whisper trigger amplifier, one of the key specifications, gain, failed in the target technology. And it was identified to be due to some of the mos transistors post migration being triode region rather than in saturation. Identifying the cause of this – the technology characteristics that caused this – and then addressing them was key to the successful outcome.

Whenever a key specification is not being met in the target technology, we have to determine which process technology or circuit characteristic is causing this. By using our automated technology analyser, we can take a design-centric approach to analyse and compare base and target technologies to see where the process technologies are similar and where they differ the most. The technology analyser considers both first and second order effects including FT, gm/id, Vdsats among others. Using this technology, we were able to identify that the target technology of 22nm had distinctly different characteristics for Vdsat(min), which was causing the mos transistors to be in a triode state.

With traditional methods, identifying this would have been time consuming, but the technology analyzer gave a clear and rapid identification of the issues – in this case a difference of 5x in the Vdsat(min) value. Looking at the gm/id curve, the device could be operated close to Vdsat(min) in the base technology, to achieve a certain value of gain. However, in the target technology, due to the larger Vdsat(min), the device required a much larger headroom to produce the same level of gain.

The solution involved removing the resistive load from the drain Idc path, making the whole process simpler. Thanks to the targeted design automation functionality, we were able to fix the topologies and ensure the GAIN_max results passed in the target technology and the circuit works.

The reality? IP reuse is not a dream or a myth

Our platform comprises three elements – Technology, Methodology and Design Expertise. Using this trifecta, we have been able to deliver IPs in different technologies, nodes and with improved characteristics.

The AMALIA technology consists of four elements: a technology analyzer, schematic porting, design enabler and layout migration.

Tech analyzer: Using a design-centric approach, the platform addresses key first and second order effects of process technologies and extracts and compares characteristics between base and target technologies to provide the user with clear inputs on how similar the technologies are.

Automated schematic porting: Taking the inputs from the analyzer and generates a circuit in the target technology. This circuit can then be verified for response and characteristics.

Design enabler: Once the circuit design for the target technology is correct, the design enabler and our team of experienced designers can nudge the circuit back into specification.

Layout migration: The final stage is focussed on putting together the base layout framework which is then expanding on by our experienced layout designers.

Who we are?

We are Thalia Design Automation. Founded in 2011, Thalia’s aim is to improve the efficiency and process cost of analog circuit design and to rollout an analog IP reuse platform. We’ve worked with vendors, numerous foundries and different nodes and have design centres in Germany and India with our headquarters in the UK. We have successfully rolled out an analog IP reuse platform that combines smart technology, a smart methodology and our smart and experienced resources to streamline the IP reuse process.

In doing all this, Thalia regularly provides customers with a time saving of around 50% compared to a traditional circuit redesign. And as I stated at the beginning of this article, achieving a faster time to market is key to maximizing revenues from any IP.