Multi-Layer Deep Data Performance Monitoring and Optimization
By proteanTecs, Siemens Digital Industries Software
Combining functional and parametric monitoring of the real-world behavior of complex SoCs provides a powerful new approach that facilitates performance optimization during development and in the field, improves security and safety, and enables predictive maintenance to prevent field failures. proteanTecs’ Universal Chip Telemetry (UCT) and Siemens’ Tessent Embedded Analytics are complementary technologies that enable just such an approach, informed by Deep Data.
Examples based on ADAS and autonomous driving systems demonstrate how the two systems interact to shine a light on even the most complex problems in electronics design, production and deployment.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
- Performance optimization using smart memory controllers, Part 1
- Optimizing embedded software for power efficiency: Part 3 - Optimizing data flow and memory
- Optimizing High Performance CPUs, GPUs and DSPs? Use logic and memory IP - Part II
- Optimizing performance, power, and area in SoC designs using MIPS multi-threaded processors
- System Performance Analysis and Software Optimization Using a TLM Virtual Platform
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow