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Scalable, On-Die Voltage Regulation for High Current Applications
Chip Design - better asynchronous than synchronous?
Solving the problem with NCL - an extended Boolean algebra.
As SoCs get bigger and performance is more demanding, the normal synchronous implementation gives designers severe problems. Synchronizing different clock domains, the current spikes generated by fast switching and contact drop inside the chip are all complex. Why not implement some or all of the design asynchronously? Null Convention Logic (NCLTM ) technology, developed by Theseus Logic, may help find the right answers.
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