English
Economics of the FPGA
By Efinix, Inc.
EETimes (October 11, 2021)
Today’s world is full of high-tech gadgets with increasingly complex functionality and capabilities that were historically the stuff of science fiction. When we use our connected devices and snap high-definition photos with our “supercomputer” cellphones, few of us give a thought to the underlying technology. Fewer still are aware of the increasing tension being created by physical and market dynamics within each device that makes every successive generation incrementally more difficult to make and to justify.
The relentless pursuit of small devices with lower power and more capability drives the need for increased integration. This, in turn, requires smaller silicon geometries wherein designers are required to adopt 28-nm, 16-nm, 12-nm, 7-nm, 5-nm processes and beyond. With every reduction in silicon process geometry comes a nonlinear increase in design and manufacturing cost. Designing in smaller geometries requires increasingly rare expertise, longer design times, increased cost of design tools, and increased program risk.
These exponentially increasing design costs must be amortized over the volume of devices shipped during the project’s lifespan. Unfortunately, as global competition increases, the diversity of application functionality increases and product life spans reduce. Fewer designs can justify the expense of custom silicon and fewer companies can attract the increasingly rare talent to design it.
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