Statistical techniques attack process variation

Statistical techniques attack process variation
By Ron Wilson, EE Times
March 6, 2003 (3:14 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030306S0042

Process integration engineers are gradually losing their battle to keep process variations hidden behind the defensive barrier of tight design rules. Variations in metal line widths, layer thicknesses, via integrity and transistor critical dimensions, while continually shrinking in absolute terms, are growing as a percentage of the increasingly minuscule dimensions they affect.

The mechanisms that lead to these variations seem to be growing in number as processes become more complex. And variations that used to appear only between wafer lots may now be seen between wafers, between dice on a single wafer or even, in some cases, across the surface of a single die.

While process engineers struggle to reduce the variations further, it is left to chip design teams to figure out what to do about the process they have, not to wish for the process it may become in 18 months. Designers engaging with 130-nanometer or 90-nm processes must have strategies for coping with these variations or risk massive yield problems.

Start at the foundry

The beginning of the solution, needless to say, is an intimate relationship with the foundry. Without adequate data there is no defense. And whether that data is already in the process design kit or whether it must be sought separately depends to some degree on the design itself.

The process design kit is intended to provide adequate information for conservative designers working on mostly digital designs. Pushing the envelope may require more data. And what happens when you ask for more data will depend almost entirely on your relationship with the foundry.

For digital designers, adequate data can be the foundation for additional, or modified, design rules to protect the design from known variations. This is in some sense cold comfort, since design rules are already bewilderingly complex, and additional data transforms for image enhancement just add to the problem.

But for the precision analog d esigner, and in particular for the RF or microwave designer, the problem is far worse. At the far reaches of operating frequency, virtually every shape is important; virtually every dimension is, if not critical, at least significant to the operation of the circuit. In this field, device sizing is a key component of design.

But analog and RF designers are also familiar with sensitivity analysis, even for discrete circuits. One of the steps in sound analog design has always been to examine the sensitivity that the critical performance metrics of the design display to variations in component values.

That has not changed with IC design, where variations in components are in fact variations in process parameters. The big difference is that the designer can't solve a sensi- tivity problem just by specifying a higher-precision or hand-selected component. The process is what it is, and if the circuit design is too sensitive to a parameter, it's the design that will have to be changed.

We follow a microwave low-noise amplifier designer through the process of testing a design against process variations. It is a multistage evaluation that is highly dependent on automated tools.

Nonetheless, by identifying sensitivities in the design, making appropriate modifications and picking target values for components that center the design in the process windows, enormous improvements in yields are possible. While this work is specific to microwave design, it is likely a foreshadowing of the sorts of things that will go on-with greater automation and at a higher level of abstraction-in digital cell design soon and in interconnect design eventually. Read and be prepared.

At the far reaches of operating frequency, virtually every shape is important.