Why you need RTL virtual prototyping

Why you need RTL virtual prototyping
By Suk Lee, EEdesign
March 28, 2003 (7:10 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030328S0053

Out of all these challenges chip designers face, timing closure has probably been the number one digital IC implementation challenge since at least 1990. What's really going on here? What's fundamentally the issue?

For digital IC designers, regardless of whether they use a COT fab, or go through an ASIC vendor, existing standard-cell or gate-array design methodology is built on a 15-year- old premise that gate delays dominate (Figure 1). The implications of this premise facilitated a convenient design methodology: initial, front-end design activity could proceed more or less independently from the process of actually laying out the chip.

In fact, the overall design process could happen in a neatly partitioned manner, with distinct steps between phases of the design. This was particularly beneficial because chips were simple, and EDA tools of the 1980's were primitive. This meant that avoiding layout until the last phase of the design implementa tion process vastly simplified the design task.

Fast forward 15+ years. Wire delay now dominates gate delay (Figure 2), and yet the same methodology prevails: estimate delays up front, hope that the estimated delays match the post-layout delays, and avoid the expensive, time-consuming layout process until as late in the design schedule as possible. The addition of synthesis into the mix actually increases the challenge by dramatically increasing the designer's ability to generate gates, while at the same time abstracting the gates themselves so that the gates become incomprehensible.

Figure 1 -- Delay estimate-based methodologies enabled by 1985 era technology

Figure 2 -- Nanometer era technology requires "wires first" design

The delay due to wires now dominates over gate delay, and the calculation of the delay caused by wiring is now laden with second and third-order issues. For example, crosstalk, which is not only wire-dependent, but dependent on placement and neighboring wire topologies, is becoming an increasing problem for both high-speed and low-power designs. How can this be estimated up front without knowing in advance what the layout will look like? The answer is alarming: it can't be.

The emergence of virtual physical prototyping

Today, the fundamental premise is the problem: front-end design can no longer be disassociated from layout issues which will impact back to the RTL, or more precisely, the design process must proceed in parallel with multiple layout implementations. In other words, the design must be prototyped as the design itself is being developed. Furthermore, the prototype must be a very close match and be correlated to the final actual implementation of the chip. A process, known as continuous convergence that funnels a prototype into the final production design must be applied.

Why hasn't this been done yet?

In a sense, it has. ASIC vendors have been running multiple trial layouts for many years, trying to anticipate what the layout would look like well before the final design was handed off from customer to vendor (Figure 3). The challenges with this are:

The trial layout process itself was disassociated from the designers so that rapid feedback could not take place.
The customer's design often changed substantially between trial layouts, making the correlation between the trial layout and actual production layout a hit-or-miss affair. The trial layout, was in effect, always lagging several iterations behind RTL design changes.
Running multiple trial layouts was costly both in time and manpower to consumers and vendors.
The design process itself still relied on estimated delays, meaning that the results of the trial layouts themselves did not correlate with the front-end design assumptions, leading designers down blind alleys .

Figure 3 - Applying nanometer-era technology with estimate-based tools

Nanometer era design requires virtual physical prototyping. It allows you to generate a real, legal placement, run a trial route that uses real detailed metal layer assignments (not just global route estimates), is easy to use, is very fast, and very high capacity, and allows you to continuously run trial layouts in parallel with the design process (Figure 4).

This technology fundamentally enables the methodology to change -- to allow designers to embrace wires early in the process and to know that the prototypes they've been running will converge to the final production design. Synthesis, design, and implementation can take place in parallel, feeding true physical information into the synthesis process.

Figure 4 - "Wires first" convergent design, from RTL to layout

Extending virtual physical prototyping to RTL

Why does physical prototyping need to be extended to the register transfer level? There are two reasons: one large-scale issue, and one at the nanometer level (Figure 5).

The large-scale issue has to do with the breadth of today's design process. Due to the enormous number of gates available with nanometer technologies, true system-level integration is now taking place. Design teams are large and segmented by skill sets. Architectural decisions may be made early in the design process that lead to problematic implementation.

In addition, system-level verification tasks, software development, and package development are proceeding in parallel with RTL development. Catching implementation issues early in the RTL coding process can lead to massive increases in productivity and reductions in overall system design implementation time.

The nanometer-level issue is that, independent of architectura l issues, the dominance of wire delays and effects may cause implementation issues even if the large-scale architectural issues have been dealt with early.

Figure 5 -- Eliminate large-scale issues early

To most effectively address gigahertz architectural issues to nanometer implementation issues, there is a need for a set of cockpits that enable a continuous convergence of design activities from design exploration to final production implementation. Furthermore, these cockpits must be co-correlated so as to ensure the process actually does converge.

Ideally, these cockpits would present design information in a form relevant to the appropriate design context (such as, don't present wire congestion maps to RTL designers!) and yet be able to inter-communicate to allow designers and implementers to effectively analyze and solve design problems that span different design paradigms.

In other words, RTL de signers shouldn't have to be layout experts and layout experts shouldn't have to be RTL designers.

Due to the dominance of wire-delay and overall wire-effects over gate delay, front-end design can no longer be disassociated from layout issues that will impact back to RTL, or more precisely, the design process must proceed in parallel with multiple layout implementations. In other words, the design must be prototyped as the design itself is being developed. Furthermore, the prototype must be a very close match and be correlated to the final actual implementation of the chip. A process known as continuous convergence that funnels a prototype into the final production design must be applied.

Designers and implementers must have the opportunity to apply a "wires first" methodology to a wires-dominated design problem. In the nanometer era it is essential that RTL designers and chip implementers be able to work collaboratively, knowing that they are using the same underlying technology, in a context that i s aligned to their respective skill sets. Tools that extend virtual physical prototyping and continuous convergence to the RTL design process, enabling macro-architectural decisions to be made in a nanometer physical context, dramatically reduce the time to convergence from an RTL prototype to a full physical implementation.

Suk Lee is vice president of solutions marketing for the IC Solutions business at Cadence Design Systems. Prior to joining Cadence in 1999 (his second stint with the company), Lee spent time with Aspec Technology as vice president of marketing, and LSI Logic. All together, he has 15 years marketing and engineering experience in top-tier electronic design and semiconductor companies, including Texas Instruments.