Weighing Chip-Design-Verification Challenges for MedTech

By Bob Smith, ESD Alliance
EETimes (November 23, 2022)

Safety and security are huge and complex chip-design-verification challenges to be dealt with for medical technology (MedTech) applications. Acknowledging this, Lucio Lanza, managing partner of Lanza techVentures, asked panelists at SEMICON West 2022 this question: How must verification change as MedTech and other new applications retarget existing chips in new ways?

Dave Kelf, CEO of Breker Verification Systems, explained verification’s three axes.

The first is the way verification is done with large chips—a move from simulation to leverage different technologies.

The second is the verification requirement—previously functional verification and the final test of the chip. Now it includes more requirements, such as SoC integration, making sure cache coherence and integration issues as well as challenges, such as safety and security, are addressed.

The third axis is the number of different applications, he said. It was communications, consumer, and computer electronics 20 years ago. Now it’s MedTech, automotive, and other new applications with large devices that need to be verified. Safety and security become important.

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