English
Weighing Chip-Design-Verification Challenges for MedTech
By Bob Smith, ESD Alliance
EETimes (November 23, 2022)
Safety and security are huge and complex chip-design-verification challenges to be dealt with for medical technology (MedTech) applications. Acknowledging this, Lucio Lanza, managing partner of Lanza techVentures, asked panelists at SEMICON West 2022 this question: How must verification change as MedTech and other new applications retarget existing chips in new ways?
Dave Kelf, CEO of Breker Verification Systems, explained verification’s three axes.
The first is the way verification is done with large chips—a move from simulation to leverage different technologies.
The second is the verification requirement—previously functional verification and the final test of the chip. Now it includes more requirements, such as SoC integration, making sure cache coherence and integration issues as well as challenges, such as safety and security, are addressed.
The third axis is the number of different applications, he said. It was communications, consumer, and computer electronics 20 years ago. Now it’s MedTech, automotive, and other new applications with large devices that need to be verified. Safety and security become important.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
- Key considerations and challenges when choosing LDOs
- Reliability challenges in 3D IC semiconductor design
- Handling the Challenges of Building HPC Systems We Need
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow