VESA Video Compression on MIPI DSI-2 Enables Next-Generation Display Applications

By Joe Rodriguez & Simon Bussières | Rambus

Over the past decade, we have seen generations of new products with increasingly sophisticated display feature sets. Each new generation pushes the boundaries of display technology even further with higher resolutions, faster refresh rates, and increased pixel depth at the forefront of these developments.

Whether it is a mobile, augmented and virtual reality (AR/VR), or automotive display, an application processor (AP) generates pixel data, which is then transported over a physical interface (PHY) to the display. As display resolutions have increased, so has the amount of pixel data transferred over the PHY. This leaves designers with the tough task of finding ways to transport all this data over current display interfaces, without compromising on cost, power consumption, and, most importantly, visual quality.

Designers can either increase the number of physical data lanes in their design, which in turn has a knock-on effect on cost, power consumption and electromagnetic interference (EMI), or they can use video compression to reduce the total bandwidth requirements. Two visually lossless display compression codecs from the Video Electronics Standards Association (VESA®), supported within the MIPI® DSI-2^SM display interface specification, let designers choose the codec that best meets the criteria of their target application.

VESA first began work on a common, industry-wide standard in 2012. VESA Display Stream Compression (DSC), was released in 2014 and was the industry’s first visually lossless video compression codec. The MIPI Alliance was the first organization to adopt the use of DSC inside its transport standard, MIPI Display Serial Interface (DSI®). While initially designed for mobile devices, VESA DSC has since been widely adopted in other display-based products including AR/VR headsets, cars, TVs, monitors, and GPUs (graphics processing units).

As display bandwidth requirements kept growing, VESA identified the need for a second compression codec that would offer additional compression capabilities, while offering the same visually lossless picture quality as DSC. VDC-M (VESA Display Compression) was announced in 2018 and MIPI Alliance was again the first organization to adopt VDC-M into their transport standard, MIPI Display Serial Interface 2 (DSI-2). MIPI DSI-2 also continues to support VESA DSC.

DSC and VDC-M are both visually lossless. This means that an end user cannot distinguish between the uncompressed original images and the compressed version. This has been proven through a series of rigorous tests conducted by VESA. Since the codecs are used across a wide range of applications, the algorithms have been designed to render excellent quality across all types of content. In 2021, additional research conducted by VESA validated the visually lossless performance of both codecs for stereoscopic 3D use cases. DSC and VDC-M are also both extremely low latency compression algorithms, a very important design characteristic, especially for AR/VR and automotive applications.

VESA DSC can compress any image to 8 bits per pixel (bpp), which results in a 3X compression ratio for a 24 bpp image or a 3.75X compression ratio for a 30 bpp image. By implementing VESA DSC, designers can typically cut the number of MIPI transport lanes in half, which translates to savings in power, area, and design complexity. For example, a mobile High Dynamic Range (HDR) display running at 4K / 60 frames per second (fps) / 30 bpp requires 16.5 Gbit/s (uncompressed) of bandwidth. To transmit the video over a MIPI DSI-2 link, using a D-PHY^SM, 8 lanes running at 2.1Gbit/sec would be required. To support 8 lanes requires two instances of the DSI-2 controller and D-PHY. With the Rambus MIPI DSI-2 and VESA DSC IP cores, visually lossless compressed video can be transmitted using only 4.4 Gbit/s of bandwidth. The MIPI link can use one instance of 4 lanes at 1.1 Gbit/s. This lane reduction from 4.4 Gbit/s to 1.1 Gbit/s comes with a significant drop in the clock rate from 562.5 MHz to a much more manageable 137.5 MHz.

VDC-M uses a set of even more sophisticated video encoding tools to achieve yet higher compression factors, all while offering the same or even better picture quality. For example, it can reduce a 30 bpp uncompressed image to 6 bpp, and in some use cases, it can be visually lossless at a 6X compression ratio. An AR headset with two displays of 5K x 5K at 120 fps / 30 bpp requires 100 Gbit/s (uncompressed) bandwidth per eye. Transmitting such high bandwidth video over a MIPI DSI-2 link, even when using the latest C-PHY^SM or D-PHY standard versions, is challenging in terms of cost, power, and potential problems with EMI. With the Rambus MIPI DSI-2 and VESA VDC-M cores, visually lossless compressed video can be transmitted using only 20 Gbit/s of bandwidth per eye. The MIPI link can use a D-PHY with 4 lanes at 5 Gbit/s.

How should designers choose which compression to use? It really depends on the bandwidth, power, and interoperability requirements of each application. As is always the case, there is also a trade-off between compression capabilities and codec complexity. While you can hit those higher compression ratios with VDC-M, the codec is larger in terms of gate count and RAM (Random Access Memory) usage due to the more complex algorithms it uses. It is expected that both compression codecs will co-exist for the near future with designers opting for VDC-M when they need to support extremely high resolutions, pixel depths, and frame rates.

Rambus VESA DSC, VDC-M, and MIPI DSI-2 IP solutions are available to help designers lower risk and achieve faster integration when creating next-generation display products. For more information, visit the Rambus VESA video compression and MIPI DSI-2 webpages.