Virage pulls back the covers to detail platforms

Virage pulls back the covers to detail platforms
By Ron Wilson, EE Times
May 5, 2003 (1:49 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030505S0042

San Francisco - Virage Logic has been offering its own notion of what a platform is since last fall. A platform, it's been observed, has become about as malleable as that proverbial elephant in a darkened room, feeling very different depending on the angle from which it's approached. To Virage, historically a powerhouse in memory intellectual property, a platform feels a lot like a closely linked collection of memory generator tools, logic cell libraries and I/O cells.

On the surface that doesn't sound like a big deal. Just about every foundry can tell you where to pick up a set of libraries for memory, logic and I/O. But some important ideas lie beneath the covers in Virage's concept, and these are just becoming apparent. The company lifted off some of those covers at last month's Embedded Systems Conference here, bringing to light important detail.

One aspect of this detail is in the pad ring-the area of a system-level IC frequently om itted from platform discussions. Virage has addressed the question of just how to make a pad ring reliable and predictable, yet extensible. The company has answered that question by, in effect, defining a set of primitives from which a variety of I/O structures can be built, both by Virage and by third-party partners.

Choosing a base set of primitives is not trivial. If the primitive cells are at too low a level, it will be entirely possible to build I/O blocks that will give major problems late in the design flow, when problems of IR drop, signal integrity and modeling inaccuracy show up. But if the cells are too complex, they will limit the flexibility of the whole structure.

Virage decided that it was possible to define such a set of primitives: location rules, isolation rules, power and ground cells, and drivers and receivers. Integrated into the library are provisions for ESD tolerance and latchup resistance. This gives partners like TriCN Inc. here the ability to build complete interfac es, such as DDR II, PCI Express, Rapid I/O and the like, in almost a plug-and-play fashion, preserving the silicon-validated device models done by Virage.

Another key aspect of the platform idea is from a component of the technology that was announced last fall: the metal-programmed logic cell libraries. In addition to performance- and area-optimized libraries, Virage offers a set of logic libraries in which the cells are all built from a single base cell and configured to their particular function by metal links. The designer can select how many metal layers he wants to use in the cell-configuring process. The more metal layers allowed for configuration, the better the cell density, but in exchange for blockages in those metal layers. But the configurable cells are substantially more routable than fully optimized standard cells, so what the designer gives up in density he may very well get back in routability.

Beyond time-saving

While the notion of a platform, particularly in this context, has been suggested mainly in terms of reducing system integration and verification times, there is another aspect to the idea that is about to draw a great deal of attention. That is the importance of a physical platform in dealing with the new crop of problems in 90-nanometer and smaller process geometries.

As has been widely discussed, the industry is entering an area of new physical-design problems. Indeed, it may have started in the 130-nm generation, but so far heroic work by a number of sources has protected all but the most advanced design teams from the results. In this area, reticle enhancement technology-necessary to form the subwavelength features of contact, poly and even lower metal layers-is beginning to vastly complicate physical design. Phase shift plates can interfere with each other, limiting the shapes that can be fabricated. Optical-proximity correction features can also interfere with each other, or can require space in the layout that has no corresponding feature o n the wafer, imposing even more limits on cell design, especially when cells are optimized for density.

Further, effects of the optical column design in the stepper-and even details of the planarization process-can limit design. The former are particularly interesting, in that they can impose so-called "forbidden pitches.''

In some of these processes, regularly spaced features cannot be permitted at particular pitches, while they are quite acceptable at other pitches. It has been suggested that as use of off-axis illumination becomes more extreme, designers may have only a few acceptable pitches instead of a few forbidden ones.

The result of all this is that design rules are becoming enormously complex. Hence, there are growing advantages to having a regular, repeated fabric of cells that are known to work with the particular process. The sort of platform toward which Virage is working-particularly with the metal-programmed cells-would be just this sort of regular fabric.

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