Fabless model proving less than fab

Fabless model proving less than fab
By Anthony Cataldo, EE Times
May 19, 2003 (12:08 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030519S0056

SAN MATEO, Calif. — Would-be semiconductor entrepreneurs are playing by a different set of rules these days. The time when, as the old joke went, all it took to start a company were four Indian engineers and an American guy to do the marketing are over, and startup chip makers are beginning to look like an endangered species.

A total of five chip companies that didn't have their own manufacturing plants were founded last year, according to the Fabless Semiconductor Association. That's a paltry figure compared with the 53 that launched in 2001 and the 92 founded in 2000. Even in 1995, before the dot-com craze, 23 chip companies took root. The rising costs of designing and producing a chip, at a time when funding is tight and the customer base more discriminating, have turned the screws.

"The fabless startup model is under stress," said Rob Chaplinsky, general partner with Mohr, Davidow Ventures (Menlo Park, Calif.). "It costs you a l ot of money to get to market and get proven silicon working. There's no room for error, and you have to run things really efficiently and pick your markets carefully so that there's revenue to justify material, labor and tools."

With the advent of dedicated foundries like Taiwan Semiconductor Manufacturing Co. in the late 1980s, young companies could focus on design and buy manufacturing capacity as needed, making them partially immune to the wild swings of the industry. Altera, Broadcom, Nvidia, Xilinx and others owe much of their success to this model. Fans of this model are also quick to point out that integrated device manufacturers are looking more like their fabless counterparts as they sell or mothball their own fabs.

But the days when design and production costs could be ignored because money was easy to come by are no more. Many young fabless companies, for example, can no longer afford the $3 million it takes to buy their own design tools, so they are contracting with ASIC vendors. But this just defers the cost by shifting it to the price of the wafer. Materials, operations and miscellaneous costs can add up to about $4 million. The big one is labor, which can run to $8 million. Factor in the uncertainties of keeping up with Moore's Law and the picture gets more bleak.

Chaplinsky said Mohr, Davidow is not closing the door to all chip companies, but wants to deal only with those that promise a big payoff. Among them are startups devising a programmable or reconfigurable architecture that can work in many applications, not an application-specific device that can attract many competitors chasing a single market. "We'll invest in a fabless company but it's got to address a $200 million to $300 million socket opportunity," Chaplinsky said.

Even more attractive, he said, are companies that don't make chips but help others do so. Among those that Chaplinsky has funded in recent months are Brion, which addresses design-for-manufacturing, and OnWafer, which deals with critical d imension control.

"The challenge is trying to achieve the same benefits of Moore's Law by extending existing technology," Chaplinsky said.

Not all VCs are this skeptical about chip startups. Irwin Federman, general partner with U.S. Venture Partners (Menlo Park), said that the problems with mask costs, physical design and power consumption that companies face as they move to 90- and 65-nanometer design rules are by no means showstoppers.

"There are technology shifts that are changing the economics of the business but I don't view that as being a deterrent for investment opportunities," Federman said. "The belief that these changes are going to affect the efficacy of silicon going forward is to be distracted."

To Federman, there's ample opportunity for young companies to develop new application-specific products, largely because it's getting so expensive for individual vendors to design their own ASICs. "The volumes for consumer and industrial products are enormous-beyond anyth ing we've seen before," he said. "It's not clear to me that the incumbents will come in and take these markets."

One powerful ally on the side of startups is TSMC, which derives most of its revenue from fabless companies and has a vested interest in helping new ones. The foundry giant plans to expand its multiproject wafer, or "shuttle," program to reduce the initial cost of silicon prototypes as one way to help startups manage costs. TSMC also wants customers to incorporate design-for-manufacturing steps into their design flow prior to GDSII, a tactic that should help avoid costly re-spins.

Startups totaled five last year, a new low, as design and production costs soared and funding nosedived.

"TSMC has a huge business to protect and they've become a critical e lement of the entire infrastructure," Federman said.

Federman said that to gain the blessing of the VC community, a startup should be able to get the job done with $25 million to $35 million, though the limit varies depending on the VC. Most say that the company should have partners or customers lined up early, and should be prepared to make a payout in three years.

"What they want to see is a company that reaches certain milestones, and if you reach them you have a better chance of coming back for more," said one president of a still-secret chip startup who recently finished a round of funding. "It's a shorter leash. You have to have a bulletproof proposition, an outstanding management team and an execution track record, and that's just to get you in the door."

That's assuming the VC in question hasn't lost faith in chip startups. "My sense is that the Irwin Federman school is alive and well, but they are still very nervous," the startup's president said.