Design-Stage Analysis, Verification, and Optimization for Every Designer

By Michael White, Siemens EDA

An innovative approach that is rapidly gaining popularity in semiconductor design is the introduction of “shift left” analysis and verification, shifting signoff-quality design analysis, verification, and optimization back into earlier stages of the design flow. Calibre shift left solutions provide innovative tools and functionality that rely on proven, foundry-trusted Calibre rule decks and engines, ensuring the highest quality of results, industry-leading performance, and user-friendly integrations and interfaces.

One of the first things an aspiring chef is taught is the process of “mise en place,” which is French for “put in place” or “gather.” Mise en place describes the method by which chefs collect and prepare all the ingredients that will be needed to make a dish. What does that have to do with integrated circuit (IC) design?

Well, having everything ready to go when actual cooking begins ensures dishes can be prepared as quickly as possible while ensuring consistency of the results. But of course, different chefs obviously have different requirements and different ingredients for their mise en place, depending on the dishes they will prepare. In the same way, IC designers all want to get to tapeout as quickly as possible with a design that is signoff-clean and optimized for manufacturing, but just like the variety of chefs in a restaurant, different types of designers have different verification and optimization needs.

An innovative approach that is rapidly gaining popularity is the introduction of “shift left” analysis and verification, shifting signoff-quality design analysis, verification, and optimization back into earlier stages of the design flow. Shift left design-stage analysis/ verification/optimization enables designers to quickly and accurately analyze layouts and resolve errors that, if left unchecked until signoff, would be immensely challenging and time-consuming to correct.

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