SoC NoCs: Homegrown or Commercial Off-the-Shelf?
By Andy Nightingale, Arteris
DesignNews (April 29, 2024)
The developers of today’s system-on-chip (SoC) devices face a myriad of decisions. Some of the early choices start when defining the overall architecture of the device. Next comes the determination of which intellectual property (IP) functional blocks to be used and their origin.
Many IPs are purchased from trusted third-party vendors, such as processors from Arm and DDR memory controllers from Cadence or Synopsys, for example. Meanwhile, the secret-sauce IPs that will differentiate this SoC from its competitors are typically developed in-house. These IPs include specialized hardware accelerators, such as artificial intelligence, machine learning, and deep learning cores.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Arteris Hot IP
Related Articles
- SoC design: What's next for NoCs?
- Accelerating SoC Evolution With NoC Innovations Using NoC Tiling for AI and Machine Learning
- SoC design: When is a network-on-chip (NoC) not enough?
- How NoCs ace power management and functional safety in SoCs
- Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
New Articles
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Synthesis Methodology & Netlist Qualification
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution