DAC panel finds IP quality lacking
DAC panel finds IP quality lacking
By Nicolas Mokhoff, EE Times
June 3, 2003 (7:53 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030603S0045
ANAHEIM, Calif. There is a silicon intellectual property (IP) "quality gap," and customers have to learn to live with the hype, according to participants at a Monday (June 2) evening IP verification panel at the Design Automation Conference here. Representatives from IP sellers and buyers shared their views on IP-based design and how it has now become commonplace, as systems-on-chip (SoCs) take hold on many applications. The verification of IP blocks, and of systems containing these blocks, remains a significant problem. Quality of IP is the number one issue, and even ROI (return on investment) has an impact on quality. "The idea is that you are buying a piece of IP so that you don't have to develop the IP in-house," said the lone IP buyer on the panel, Thierry Pfirsch, Core Competence Manager for Intellectual Property at Alcatel. Pfirsch said that the documentation on the IP you are buying needs to be available, and what's more, it m ust be executable. He warned that IP providers need to get their ducks in a row, because buyers are only going to limit themselves to dealing with at most three providers. Senior vice president of technology at Verisity Michael McNamara commented that the quality of IP has increased from year to year for last three to four years, but for IP to be really accepted "you need verification of the IP at the system implementation level." But system verification requires tuning the IP to suit the system requirements, he said. Debate raged about kind of IP can be fine-tuned to system needs and what kind can't. Michael Kaskowitz, general manager of Mentor Graphics' Inventra division offered this: only standard IP can be mucked around with. "The Star IP (CPUs and memory) are untouchable, and the library IP is tied to the process, and you don't want to mess with that." Phil Dworsky, director of marketing in the DesignWare Star IP Program at Synopsys, remarked that there are instances that may call for tweaki ng IP for customers to meet their needs but that in general, "IP is about scalability, and should not be adjusted to meet individual customer's needs." Verification then becomes a nightmare, he said. The panel was sponsored by the Alba Centre, in association with Scottish Development International, and Skye Marketing Communications. The Alba Center was formed to develop Scotland as a leading world location for system level integration technology, in partnership with four of Scotland's top Universities in this field (Edinburgh, Heriot-Watt, Strathclyde and Glasgow). This partnership has recently started the Institute for System Level Integration with an online "Introduction to verification" curriculum program. Classes start Sept. 8, 2003.
Related Articles
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- Synthesis Methodology & Netlist Qualification
- Streamlining SoC Design with IDS-Integrate™
E-mail This Article | Printer-Friendly Page |