Accelerating RISC-V development with Tessent UltraSight-V

By Francisca Tan, Product Management Lead – Tessent Embedded Analytics

Siemens’ longstanding and deep engagement with the RISC-V community dates back to the foundation’s early days. Involved initially as the independent company UltraSoC, now as Siemens EDA, Siemens has played a significant role in shaping the RISC-V ecosystem, mainly through technical contributions and ongoing participation in relevant working groups. We actively and extensively contributed to developing the RISC-V ecosystem, making key technical contributions to the RISC-V Efficient Trace (E-Trace) standard.

Our involvement continues today through our engagement with the RISC-V Debug Trace and Performance Monitoring special interest group. SoC debug is becoming increasingly challenging as the complexity of multi-core systems on chips (SoCs) continues to grow. Debugging and optimizing software for these systems is escalating, increasing development time, effort and cost. There is a critical need for more efficient and scalable debugging methods to help engineers quickly identify and resolve hardware and real-time software issues.

Tessent™ UltraSight-V is a complete end-to-end solution for RISC-V debug and trace, designed to meet the official RISC-V E-Trace specification. This embedded IP and software solution provides comprehensive, efficient debugging and trace capabilities that integrate with industry-standard tools to empower embedded software engineers in developing high-performance embedded software.

Part of the Tessent Embedded Analytics product family, Tessent UltraSight-V uses effective, non-intrusive techniques such as highly-compressed encoded processor trace based on the Efficient Trace (E-Trace) standard, logging, high-speed interfaces (USB 2.0) and DMA for fast code uploads. This solution minimizes debugging delays and accelerates SoC projects, enabling you to meet your market deadlines.

A highly compressed trace solution for RISC-V processors

Complex systems are prone to imperfect software behaviors. Tessent UltraSight-V’s Enhanced Trace Encoder (ETE) provides a mechanism to monitor a CPU’s program execution in real time. It encodes instruction execution and, optionally, data memory accesses. It also outputs trace in a highly compressed format, significantly saving bandwidth especially in large complex systems. The device execution can be fully reconstructed offline. The non-invasive ETE works with minimal latency, so it does not affect performance.

Filtering the trace can help you investigate a problem further. The Enhanced Trace Encoder supports all the mandatory and optional capabilities in the E-Trace specification. It can also provide cycle-accurate trace, which can provide insight for software performance optimization.

A complete debug and trace solution for RISC-V processors

Tessent UltraSight-V includes a set of IP modules and host software that provide extensive visibility into how the software application behaves in the system. The Processor Analytic Module provides run control capabilities. The Direct Memory Access IP module allows code to be uploaded to the SoC 70-100X faster than normal GDB load. The Static Instrumentation IP module allows printf-style debugging with timestamps to be accomplished with 20X fewer instructions. The Virtual Console module provides a bidirectional communication channel between software running on the target and the debug host. It replaces conventional UART-based communication with no need for an additional physical port. A scalable dedicated infrastructure ensures non-intrusive monitoring. This infrastructure is accessed through USB, JTAG or PCIe interfaces. The host software in UltraSight-V integrates with GDB, OpenOCD and common IDEs such as VS Code.

In conclusion

In summary, Tessent UltraSight-V is a comprehensive debug and trace solution for RISC-V processors that combines embedded IP and software to enable efficient debugging and tracing while integrating with industry-standard tools to support the development of high-performance embedded software.

Key points include:

It is a complete solution for RISC-V debug and trace.
It is designed to meet the official RISC-V trace specification.
It is an end-to-end solution consisting of embedded IP and software.
It provides comprehensive and efficient debugging and trace capabilities.
It integrates with industry-standard tools.
It empowers embedded software engineers to develop high-performance embedded software.

Siemens' deep expertise and leadership in RISC-V debug and trace solutions are reflected in Tessent UltraSight-V's capabilities.

For more information on Tessent UltraSight-V and other embedded analytical solutions from Siemens EDA, please visit:

https://eda.sw.siemens.com/en-US/ic/tessent/embedded-analytics/ultrasight-v/