Optimizing 16-Bit Unsigned Multipliers with Reversible Logic Gates for an Enhanced Performance

By Pankaj Singh, DFT Engineer, eInfochips LTD.

Abstract— Multipliers are crucial components in processors and arithmetic logic units. The performance of microsystems, microcontrollers, and DSP processors is often evaluated based on the number of multiplication operations performed in a unit of time. This paper compares the VLSI design of several types of multipliers used in digital electronics. Binary multiplication is one of the most complex operations in digital design and implementation, making it a popular research field in VLSI. Reversible logic gates are essential for future designs as they reduce circuit entanglement and maintain information integrity. These gates map input patterns to unique output patterns, reducing area and delay in multipliers. The multipliers discussed in this paper may find applications in Fast Fourier Transform algorithms, DSP imaging, and wireless communications. The Verilog coding of these multipliers using a full adder module made up of reversible logic has been done on Xilinx 14.6 ISE and implemented on SPARTAN 6 FPGA.

Keywords: Reversible logic, Peres gate, Feynman gate, binary multipliers, FPGA.

Introduction

Multipliers are the widely used digital parts in digital integrated circuitry and are the essential part of ALU and DSP Processors. Along with the improvement in technology, researchers are trying to design multipliers which attain either high speed, less area, or the lesser multiplication time in all of them. In this article, the design of multipliers such as an Array multiplier, a Wallace tree multiplier, a Vedic multiplier are executed, implemented, and are compared based on the parameters such as area and delay. This article uses the concepts of a reversible logic gate for the construction of multipliers. Lower area demands have become a very pivotal requirement in VLSI system design. Novel approaches are under development to design less delay, less area multipliers at industrial, physical, circuitry and logic levels. Although multipliers are the slowest component in a processing system, the multiplication method performance is decided by performance of the full adders and arrangement of parallel adders, if used. Therefore, reducing the delay and area of a multiplier could be a major task nowadays. Although, space and delay units are typically conflicting parameters such that the reduced delay gives up a larger area and vice-versa. Therefore, a bargain has to be achieved for both the delay and the area for the improvement of multiplier circuitry.

I. Theory

A. PRINCIPLES OF REVERSIBLE LOGIC GATES

Reversible circuitry: A logic gate circuitry is reversible if, the total number of inputs and the total number of outputs are equivalent to each other, and the one-to-one accord is present between all inputs and all outputs.

Constant inputs (CI): It is the number of inputs that are to be upheld as a fixed constant at either 1 or 0 to incorporate the given logical function. It should be at the minimum in a circuit.

Garbage outputs (GO): It is the number of unused outputs shown in a reversible circuitry. We cannot avoid the garbage outputs as these are required to achieve a reversiblee nature. As it is required to make a function of m input and n output reversible.

Quantum cost: It is the cost of a circuit in the terms of cost of primitive gates (1*1 or 2*2), the cost of primitive gates begins with 2*2. Cost of any 1*1 gate is 0 and 2*2 gate is 1. [2]

Flexibility: It is used to measure how efficient a given reversible logic to perform different logical functions.

Density of circuit: It is the number of operations required to realize a function such as: AND, OR, EXOR, etc.

Design constraints: Some of the design constraints are:

There should be a minimum constant input and garbage output.

The quantum cost should be low.

No fan-outs are allowed.

A minimum gate level complexity is required.

A. ARRAY MULTIPLIER

An array multiplier is a digital combinational circuitry designed for multiplying two binary numbers by applying an array of full adders and half adders wherever they are required. The array is utilized for the synchronous addition of the various partial product terms involved. We are using binary adders for the construction. The array multiplier is executed by simply shifting and accumulating the various partial products involved. The various partial products are added by a simple adder. It utilizes wires that go from one full adder to other full adders horizontally, diagonally, or vertically as needed by the circuit.

Fig. 1: Block diagram of an Array multiplier

Fig. 2: Internal RTL of an Array Multiplier

B. WALLACE TREE MULTIPLIER

The quantity of hardware needed to perform this design of multiplication is huge, but the induced propagation delay is exceptionally low. It utilizes a collection of full and half adder (wherever they are required) to the sum induced partial products in some stages unless 2 numbers are left, which are finally added by a binary adder, and which is responsible for most delay in the multiplier. Wallace multipliers diminish the delay as much possible on each successive layer. This segment of multipliers is hinged on a reduction Wallace tree in which the distinct pattern of confining of a partial product can be completed. In a tree multiplier, the partial sums are systemized in a treelike design, compressing both the analytical path and the number of adders required.

Fig. 3: Dot representation of a Wallace tree multiplier

Fig. 4: Internal RTL of a Wallace Tree multiplier

C. VEDIC MULTIPLIER

Vedic multiplication structure is built on the sixteen Vedic sutras that is easier to understand as compared to conventional mathematics. Out of these sixteen Vedic Sutras the Urdhva-triyakbhyam sutra is compared in this article, and it is a broad multiplication expression that is relevant to all instances. It figuratively means vertically & crosswise. In this technique the partial products and their sum is calculated parallelly and hence it is independent of the clock frequencies. Therefore, the major advantage is that the processors having multipliers will operate at smaller clock frequencies and thus the power consumption is also reduced.

Fig. 5: Block Diagram of a Vedic multiplier

Fig. 6: Internal RTL of a Vedic multiplier

II.IMPLEMENTATION

This section shows the proposed full adder and half adder module which are to be used in the binary multipliers. Here we have implemented different adders using several types of reversible gates like Peres and Feynman gates and then using these gates, different multipliers were implemented.

A. Proposed Half Adder:

This half adder is constructed using a single Peres gate.

Fig. 7 Internal RTL of a reversible half adder

It is a 3*3 reversible logic circuit. This gate can be utilized as a half adder module. The input design and output design of a Peres gate are given as inputs (a,b,c) and outputs (x,y,z) and the equations by which these inputs and outputs are related as given below:

x = a; (1)

y = a or b; (2)

z = (a and b) xor c; (3)

B. Proposed Full Adder

This full adder is constructed using two Feynman gates and a multiplexer.

Fig. 8: Internal RTL of a reversible full adder

A Feynman Gate is a 2*2 reversible logic circuit. This gate placed in the above figure along with a multiplexer can be used as a full adder. The input and outputs of Feynman gate are as follows:

Inputs are (a,b ) and outputs are (x,y)

x = a; (4)

y = a xor b; (5)

C. Proposed Array Multiplier

The Array multiplier has been implemented with a reversible half adder and a reversible full adder.

Fig. 9: Internal RTL of proposed an Array Multiplier

D. Proposed Wallace Tree Multiplier

The Wallace Tree multiplier has been implemented with a reversible half adder and a reversible full adder.

Fig. 10: Internal RTL of a reversible Wallace tree multiplier

E. Proposed Vedic Tree Multiplier

The Vedic multiplier has been implemented with a reversible half adder and a reversible full adder.

Fig. 11 Internal RTL of a Vedic Tree Multiplier

IV. PERFORMANCE PARAMETERS AND SIMULATION SET-UP

The 16*16 bit reversible multiplier is correlated to a non-reversible 16*16-bit multiplier, supported on the pperformance factors like propagation delay, and area (slice LUTs). To accomplish a finer performance, the circuitry designed used reversible gate modules.

Table 1. shows the comparative experimental results of a 16*16 reversible multiplier using reversible logic styles and the conventional method multiplier with reference to the area and delay product after implementing on SPARTAN 6 FPGA. The simulation of the multiplier has also been studied and shown.

Fig. 12: Simulated result of a multiplier using a reversible gate

Table 1 shows comparative results of a 16 * 16-bit multiplier

V. RESULT AND DISCUSSION

We compared three kinds of 16-bit multipliers which are an array multiplier, a Wallace tree multiplier, a Vedic multiplier. The multipliers were designed by using a full adder as non-reversible(original), a reversible full; an adder by Feynman gate. The area and delay were calculated and multiplied, and the following result was obtained. It has been determined that

a 16*16 reversible multiplier is better than 4*4 conventional multipliers.

Fig. 13: shows chart comparison of multipliers

VI. CONCLUSION

Multiplication forms the most essential procedure. Therefore, the design plan of a fast and a low area multiplier straightaway results in the enhanced speed of the device for quicker machine computation purposes as well as for a better life. From the analysis of the above multipliers, it can be concluded that a Wallace Tree multiplier is the most efficient multiplier in parameters of area and delay, followed by a Vedic multiplier and and Array multiplier. A Wallace Tree is highly efficient in parameters of speed and area and can be further used in future work appropriately. It has also been determined that a 16*16 reversible multiplier is better than 4*4 cconventional mmultiplierss.

REFERENCES

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Author Bio:

Pankaj Singh is a DFT Engineer with 3 years of experience. He has been involved in various DFT projects, specifically focusing on 5nm technology, for esteemed clients such as Broadcom and Microsoft.

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