Metal layers a key to interconnect delay?

The interconnect dilemma affects programmable logic companies at an increasing rate as they march down the process technology road map. RC and cross-chip delays of time-critical global and long routes are critical issues to be addressed to ensure that programmable logic devices continue to be embraced as a pervasive technology for digital IC designs.

How do programmable logic companies cope with these phenomena, and what novel methods are used to address them? Engineers at QuickLogic are using techniques that reduce RC delay s on nets critical to achieving timing closure of performance-intensive designs.

A fundamental characteristic of programmable logic is that a single IC is designed and manufactured for use by thousands of different customers. The architecture of these devices is generally an array of homogeneous cells connected by either a common routing pool or by segmented, hierarchical routing. Most complex programmable logic devices (CPLDs) have a fixed routing structure connecting logic cells to one another; this architecture is fast and predictable, but adds significantly to die size as the logic array increases.

FPGAs tend to have a more segmented routing structure; this architecture does not contribute to die size as much as with CPLDs but it is possible that signals on a die will take a more indirect path when routing logic. As FPGA and CPLD manufacturers move to smaller process geometries to reduce die size and cost, and increase performance, they must not take for granted or ignore the effect this move has on the delays attributed to the interconnect.

Our analysis is based on the equation for interconnect resistance, R = ( L / A, where ( is the resistivity of metal, L is the length of wire and A is the cross-sectional area of the wire. A is the product of the width, W, and the height, H of the interconnect.

In 0.25-micron process geometry and larger, the global and long routes in QuickLogic programmable devices are located on the upper layer of metal. This was advantageous for two reasons. First, the upper layers of metal are typically sparsely populated, increasing spacing between interconnects and therefore reducing performance degradations triggered by the sidewall capacitance between parallel adjacent lines. Second, the upper layer of metal is usually thicker than the lower layers of metal. Thicker metal lines allow for more cross-sectional area of interconnect, and, consequently, lower resistance.

As our engineers advanced to 0.18-micron process geometry, the width of the interconnect scaled down with the technology factor. On one hand, the scaling of the transistor widths meant that gate delays would be faster. On the other, the scaling of the interconnect width meant that the cross-sectional area would decrease and overall resistance would increase.

A secondary effect of the scaling of the technology factor was decreased spacing between interconnect wires and, therefore, increased sidewall capacitance. To ensure the highest performance possible out of our silicon, the engineers needed to make design improvements other than simply scaling the technology to improve both the resistance and capacitance of the interconnect.

The first area to attack was the resistance of interconnect. The team had the ability to add a sixth metal layer to the semiconductor topology from the five-layer metal 0.25-micron process we had used previously. To reduce resistance, it was necessary to inc rease the cross-sectional area. This was achieved by "strapping" a duplicate wire on Metal 6 to the existing wire on Metal 5 through plugs on both ends of the wire. You can imagine that strapping has the same effect as having two resistors in parallel; the effective resistance is now the product of the wire resistances divided by the sum of those same resistances.

Note that the height of the wire on Metal 5 is less than the wire on Metal 6, but the overall resistance is substantially reduced as a result of strapping the two together. The advantage of strapping is that the effective line pitch remains the same, which minimizes the need to redraw other layers. In fact, in our case, the strapping was performed by an automated layout tool from Rubicad.

The second area to attack was the sidewall capacitance of the interconnect. Sidewall capacitance rears its ugly head in the form of crosstalk between adjacent wires. The relative distance between the two wires impacts exactly how much sidewall capa citance exists. We mentioned previously that the upper layer of metal is typically sparsely populated; why not move some of the adjacent interconnect wires from Metal 5 to Metal 6 to increase spacing between the two wires? The process of moving portions of the longer-length interconnect to a different metal layer (i.e., reduced sidewall capacitance) was far more straightforward than moving to a copper-based interconnect, since the exercise was more design-intensive than process-intensive.

In moving from 0.25 micron to 0.18 micron, we only needed to add one more metal layer to achieve our performance targets. We can see that at smaller geometries we will have to use the same techniques on other metal layers to reduce their resistance and capacitance. In essence, we are "going vertical" to maintain design performance in the face of technology's horizontal shrinks.

To optimize the overall performance of the F PGA, our engineers exploited additional metal layers to reduce both interconnect resistance and capacitance. Moving the longer, global and time-critical interconnect wires to additional metal layers reduced sidewall capacitance by increasing the spatial distance between adjacent interconnect signals.

Furthermore, interconnect resistance on longer interconnect was reduced by strapping the signals: adding redundant interconnect on consecutive metal layers connected by metal plugs. These techniques allowed the engineering team to deliver high-performance products without unnecessarily increasing the risk we would have incurred by moving to more exotic metals for interconnect.

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