ASICs demand test perspective

Design-for-testability (DFT) decisions are made early in the design, along with plans for test development, test verification, and production test strategies. A DFT methodology that is well-integrated with the design tool flow allows for optimal trade-offs among performance, area, power and testability. A strong case can be made for the inclusion of test and testing elements-everything from on-chip DFT structures to the testers that will be used at various stages of production to in-field system debug and diagnostics-as essential components of the chip architecture specification.

The key to the success of this test-aware approach to chip design is a thorough understanding of the entire scope of the test activities that the chip will participate in during its life cycle. Unfortunately, the average chip designer has only a passing familiarity with chip test and characterization issues and often has no notion of board test, system test, or field test and diagnostic practices. Not only are opportunities for synergy lost to such ignorance, but simple and easily preventable mistakes are often made because of it.

For example, the ability to execute a small set of chip-level internal scan tests within a board or system environment could provide valuable feedback about the health of a given ASIC. But, unless that objective is made clear to the chip designer, the hooks required in the chip likely won't be included. A clear understanding of the needs of downstream test and diagnostic processes, however, will enable the chip designer to "architect in" the proper test structures.

The process of thinking th rough all the test-related issues up front has one other key advantage: It spurs the identification of potential holes in the test strategy early enough to allow them to be addressed. In particular, new technologies often exceed the capabilities of existing test and tester solutions. The early identification of such test holes allows the chip designer or the test provider time to react and put solutions in place.

One recent example of such a success in the early identification of a test hole is the rapid development of IEEE standard 1149.6, which enables boundary scan testing of ac-coupled nets and enhances the testability of differential pins. This is clearly a case where the existing test method (IEEE 1149.1 boundary scan) lacked the ability to deal with a trend in board design (ac coupling of high-speed nets).

But chip designers working in a vacuum had no incentive to add hardware to help deal with this problem; in fact, they probably would have preferred to have jettisoned existing test h ardware to help reach performance goals. Board designers, meanwhile, were resistant to including access points for traditional board test probes. So board manufacturers were left with a very difficult testing problem.

The ultimate solution developed by the 1149.6 Working Group involved very low-impact changes to the low-level I/O circuit design that allowed much of the board and system test infrastructure to be leveraged. The combination of chip-design, chip-test and board-test experience proved to be crucial in finding the best solution.

Jeff Rearick is an engineer/scientist for the ASIC Products Division of Agilent Technologies Inc. (Palo Alto, Calif.).