Keys to reconfigurable SDR system design

In the first, the module design must accommodate all the permutations required for system performance. This is feasible in systems with narrow operating ranges, but not for those requiring reconfigurability across complex standards. The second technique is ideal when particular algorithms have similar functions, but different implementations. And the third technique is useful when most system operations differ and require separate implementations.

A design combining processors and FPGAs is flexible enough to acc ommodate all three reconfiguration techniques, making it optimal for SDR applications. The processor can dynamically switch between major sections of software when switching between standards, while the FPGA can be completely reconfigured to implement an architecture customized for particular standards.

It is critical to optimize the trade-offs in processor/FPGA partitioning and determine which subsystems should be implemented in parameterized vs. full replacement modules. A combined FPGA-processor-based implementation facilitates optimal partitioning between software and programmable hardware.

Partitioning the system
The first step in system architecture design is identifying reconfigurable and fixed system functions. Fixed components include specific interconnect and backplane technology, power supplies and various physical-interface support. All other electronics require reconfigurability. All digital logic components other than standalone memory and storage devices can be effect ively implemented in either processors or FPGAs.

Next, the designer must identify the types of operations required and the optimal processing approach for each. These divide logically into system control and configuration and signal-processing and data path control.

System control and configuration maintain and control the system's state. These control-flow-intensive tasks require complex software implementations with little computational load and generally are performed by control processors. In contrast, signal-processing data path and control operations typically make up the bulk of the processing load. Systems with light processing demands can be implemented in software, while those with heavier loads are best implemented in a software-plus-hardware system combining DSP- and FPGA-based architectures.

Typical SDR architectures will implement the system control, configuration and the signal-processing data path using a combination of microcontrollers, FPGAs and programmable DSPs. Th e microcontroller controls the system; the FPGA and DSP handle the high-rate data-flow processing.

The partitioning between the FPGA and the DSP depends on system bandwidth. For example, a DSP can handle all the processing for low-bandwidth systems, such as FM and voice TDMA, while an FPGA will handle the majority of processing in wideband systems.

A typical programmable narrowband system uses an FPGA to perform the high-computational-load filtering and digital download conversions that cannot be handled by a DSP. In most narrowband systems, the majority of the processing capability is consumed by filtering operations. These operations can be computed much more efficiently on dedicated hardware coprocessors, while the light-load baseband processing is generally handled by the DSP.

In the typical wideband system, on the other hand, the FPGA performs the majority of the physical-layer processing, leaving only the symbol processing to the DSP. The signal-processing requirements of such s ystems can be delivered at least 10 times more efficiently with an FPGA as opposed to a DSP. In other words, a single FPGA can handle the same processing load as 10 DSPs, delivering considerable benefits in terms of power, system cost and system footprint.

Although many commercial radio applications implement these same wideband systems in ASICs, the trend has been to move back to FPGAs as the wideband standards continue to evolve and the costs of designing and maintaining ASIC-based systems continue to rise exponentially.

The proposed architecture for an SDR system includes a microprocessor, a DSP and an FPGA. By their nature, SDR systems must support many different radio standards. Developing and supporting these standards-a key requirement of SDR architecture-can be easily accomplished with the proposed architecture.

In SDR radio operations, switching between standards requires the control plane on the microprocessor to reload a new image onto the FPGA and initiate code branches wi thin the processor and the DSP to support the new standard. As such, the programming for each standard becomes an independent development that is focused solely on that particular standard. FPGAs with DSPs and microcontrollers can easily be combined into an optimal platform to support narrowband through wideband wireless standards for SDR applications.

Paul Ekas is senior DSP marketing manager at Altera Corp. (San Jose, Calif.).

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