Collaborating to deliver open licensing for IBM PowerPC cores

When IBM® decided to pursue an open-licensing model for their PowerPC® architecture, they also chose to work closely with Synopsys to improve the reusability of the cores and provide a delivery and support channel. Dean Parker – PowerPC Licensing Manager for IBM Corporation, and Phil Dworsky–director of marketing, Synopsys DesignWare® IP, explain the synergies between the IBM and Synopsys programs, and the resulting business and technical benefits delivered to customers.

The IBM PowerPC architecture has enjoyed consistent success in many embedded applications over a number of years. The performance and power efficiency of the architecture has led to its widespread use in networking, communications, consumer electronics, and many IT applications.

There is an increasing demand for higher-performance and more power-efficient processing within other embedded systems segments as well. In applications such as industrial control, medical, and automotive, more and more connectivity is being added to enable high-bandwidth communication between related sub-systems. DSP-based applications such as set-top boxes and graphics controllers are also turning to 32-bit processor cores to handle more demanding system management tasks. Overall the SoC/ASSP segment represents a growing opportunity for embedded IP suppliers. The net result is a trend for increased performance demands on the embedded processor core.

In terms of performance and power efficiency, the PowerPC architecture answers these new requirements. However, until recently, access to the core within a SoC design context has been limited to standard products and ASICs from IBM.

Open Licensing Key to Flexible Use
The key additional requirement to expand further acceptance of the PowerPC architecture, especially for the new opportunities, is to ensure that PowerPC cores are widely available and easy to use in SoC designs. The combination of an open-licensing program for the PowerPC architecture and the Synopsys DesignWare Star IP Program enables both of these key requirements.

By providing open licensing options, customers benefit from greater flexibility in manufacturing, second sourcing and a choice of design-in options. IBM is offering PowerPC technology in single-project or multiple-use licenses, and synthesizable or technology specific (hardened) designs, which results in a vast array of choices to design and manufacture PowerPC core-based chips.

Synopsys Enables Ease-of-Use
IBM recognizes that planning design for reuse around a repeatable methodology is a critical requirement for licensees targeting SoC implementation. Synopsys provides the most widely used IP in the world through its DesignWare family of products, and is the leading provider of standards-based IP. In addition, substantial expertise in developing reuse strategies for complex designs, working with several leading partners through the Star IP program, makes Synopsys a strong partner in this initiative. Working together brings benefits to designers using the IBM PowerPC architecture as well as for IBM and Synopsys, both in technical terms, and at a business level. At a technical level, Synopsys enables robust design reuse and furthers IP interoperability for the PowerPC core, as well as providing a worldwide support and delivery channel.

DesignWare Star IP Program
Re-design for reuse is a core competence within Synopsys. Within the Star IP Program, Synopsys has applied design for reuse skills to partner company’s Star IP cores, to help ensure the reusability of those parts. Other companies that want to offer their own IP to a broader market typically use this service. This includes semiconductor and fabless companies, as well as OEMs that have developed high-value IP. Addressing design for reuse issues includes the following:

• Making IP portable (synthesizable), able to target designer’s desired process technology
• Ensuring a smooth design flow
• Adding bus bridges, as necessary, for easy interface to DesignWare and other third-party IP
• Packaging with Synopsys coreBuilder tool for easy reuse with coreConsultant, which helps to automate implementation of the core.

Successful re-design for reuse enables IP to be packaged for efficient and cost-effective deployment in other designs and process technologies.

Flow for Re-designRe-design for reuse encompasses many aspects of design and process flow. At the heart of the Synopsys approach are the coding and design guidelines that are documented in the Reuse Methodology Manual (RMM) [1]. Adhering to these may mean that some updates to the design may have to take place, to ensure testability, for example. Another issue is ensuring that the design is compatible with the overall design flow and the specific point tools to be used, for example, within synthesis or verification steps.

Typically, a verification environment will be delivered with the IP design, to assist SoC designers to validate the integration task.

Although the design flow has been optimized for the Synopsys Galaxy Design Platform and Discovery Verification Platform, the DesignWare Star IP coreKit environments are founded on the premise of tool interoperability using established standards, enabling other point tools to be readily used, as appropriate.

Reuse for IBM PowerPC 440
The IBM PowerPC 440 core is the first PowerPC core to be introduced through the Synopsys Star IP program. The IBM open license provides the potential to target manufacture to any silicon process of the designer’s choice. Cores can be implemented through synthesis, or pre-hardened core implementations will also be available from leading foundries (for example, the TSMC and Chartered 0.13-micron processes).

The Synopsys re-design has optimized the DesignWare IBM PowerPC 440 core for a synthesis-based flow that targets a worst case operating frequency of 400MHz in 0.13-micron technology. The primary aim has been to deliver an automated, smooth flow through the Synopsys Design and Verification Platforms. The design flow includes Design Compiler and Physical Compiler in combination with DesignWare Library to deliver high performance results. It also supports the use of Synopsys DFT Compiler to implement flexible industry-standard test structures, as well as Power Compiler for optimizing power.

Connectivity options for SoC integration
The ability to easily interface with other sub-systems and peripherals is one of the primary considerations for reuse within a SoC context. IBM’s CoreConnect™ and ARM’s AMBA buses are the most widely used and supported on-chip bus protocols for seamless integration with commercial third party IP.

The DesignWare IBM PowerPC 440 utilizes a CoreConnect bus interface giving high-performance integration between the CPU and primary cache memory, along with an AMBA bridge that facilitates integration flexibility at the SoC interface. In addition to the AMBA microprocessor sub-system, Synopsys DesignWare Library provides a configurable bus generator and verification IP for ensuring compliance with the bus protocol and a suite of peripherals that are common to virtually every design. (Figure 1)

Figure 1. PowerPC 440 SoC Architecture from Synopsys

This approach leaves designers to focus on adding value to their design through developing original, system-differentiating functions, rather than having to re-invent the wheel re-creating standard functionality for every design.

DesignWare Star IP Deliverables
Synopsys makes the DesignWare Star IP Design View deliverables freely available to current DesignWare Library licensees; the Design View includes simulation and timing models for the core (in an industry standard semiconductor process) as well as extensive documentation, allowing designers to evaluate Star IP blocks without having to engage with the IP provider.

In order to take a design to manufacture, the customer negotiates a manufacturing license with the IP provider, in this case IBM. Synopsys then supplies the Implementation View of the core (including source RTL) to the customer and supports their use of the Star IP for implementation and verification, in the same way as any other DesignWare part. Additionally, Synopsys offers optional design services, such as core hardening and system integration.

Powering Forward
Open access to leading edge IP is a requirement that has become fundamental to many companies in delivering high-quality SoC designs.

For IBM, taking advantage of expertise within companies like Synopsys to deliver a technical and business solution for customers is seen as key to achieving success in new segments and applications. IBM continues to invest in the PowerPC architecture, including the migration to new processes as they come online, to deliver even higher-performance and lower-power devices.

About Synopsys DesignWare IP The world’s most widely used IP which includes the following DesignWare Library–Synthesizable and simulation components for datapath, memory, building blocks, and AMBA bus and microprocessor sub-system DesignWare Verification Library–Advanced verification IP for the most popular bus and I/O standards DesignWare Cores–For connectivity such as USB and PC families, available on a per-use basis DesignWare Star IP–High-value IP made available through partnerships with leading semiconductor partners and OEMs

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Dean Parker is currently PowerPC Licensing Manager for IBM Corporation.

Phil Dworsky is director of marketing for Synopsys DesignWare IP.

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