ASICs becoming SoCs

But for some reason, that doesn't seem to be happening. Companies keep designing chips. Few chip designers or design automation veterans are selling up and entering medical school. Something must be wrong with the analysis.

As a matter of fact, vendors already are offer ing a slew of ideas to address the problem. And they are discovering that there isn't just one: The rising cost of ASICs has several contributing factors, each with its own potential solutions.

There are design costs, of course. EDA vendors are attacking these by moving to higher levels of abstraction, by facilitating reuse and by pushing for system-level design languages and tools. Less obviously-but more to the point, according to the statistics-are verification costs. The EDA industry has responded with rapid shifts in verification methodologies, but in this case the design community seems to have been its own savior, moving to often quite complex blends of simulation, emulation, FPGA-based prototyping and early use of structured ASICs to carry the verification process from the very beginning of the design through production.

Then there are the physical-design and manufacturing costs: the difficulty of closure, the cost of creating the huge data sets for 130- and 90-nanometer designs, spir aling mask costs and huge minimum production runs.

The range of papers in our section this week only hints at the diversity of approaches and the degree of creativity the industry is applying to the problem.