55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
Introduction to the Philips’ LPC 2100 ARM 7-based microcontroller – the first standard microcontroller to integrate ARM-7 – and the first to use Philips’ new Memory Acceleration Module
Trevor martin gives a developer’s view of Philips’ LPC 2100 ARM 7-based microcontroller – the first standard microcontroller to integrate ARM-7 – and the first to use Philips’ new Memory Acceleration Module.
Since its inception the ARM7 core has primarily been available as an IP core for incorporation into custom System on chip designs. With the launch of the LPC2106 the first member of the LPC2100 family Philips has introduced a standard chip featuring the 32-bit ARM7 processor on chip FLASH and SRAM with a range of general purpose peripherals in low pin count packages. However this on it own does not necessarily make a successful microcontroller, as always the devil is in the detail and this article will look at some of the key features of the LPC2100 family that help to successfully integrate the ARM7 CPU into a standard microcontroller architecture.
Related Articles
- An introduction to ARM Cortex-M0 DesignStart
- What next for microcontrollers?
- Reinventing JTAG for SoC debugging
- ARM provides the microcontroller solution
- ARM Security Solutions and Intel Authenticated Flash -- How to integrate Intel Authenticated Flash with ARM TrustZone for maximum system protection
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- System Verilog Assertions Simplified
- Smart Tracking of SoC Verification Progress Using Synopsys' Hierarchical Verification Plan (HVP)
- Dynamic Memory Allocation and Fragmentation in C and C++
- Synthesis Methodology & Netlist Qualification
E-mail This Article | Printer-Friendly Page |