English
Configurable Processors: Ready for Prime Time
By David Fritz, ARC International
The configurable processor has been around for some years, with the promise of improved performance and reduced power consumption and real estate area. But is only recently that its promise has begun to be matched with design and verification tools. David Fritz looks at today’s options.
The configurable processor has been around for some years, with the promise of improved performance and reduced power consumption and real estate area. But is only recently that its promise has begun to be matched with design and verification tools. David Fritz looks at today’s options.
Related Articles
- Hit performance goals with configurable processors
- Creating multi-standard, multi-resolution video engines using configurable processors
- Configurable Processors for Video Processing SOCs
- Configurable processors or RTL -- evaluating the tradeoffs
- Tuning Fork - A Tool For Optimizing Parallel Configurable Processors
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
|
E-mail This Article | 
|
|
Printer-Friendly Page |