Optimizing power-management IP integration in 3G SoCs

The rapid proliferation of third-generation mobile phones challenges semiconductor companies to integrate as many analog, mixed-signal and digital functions into a single system-on-chip (SoC) as possible. However, to meet the power demands of emerging multimedia-enabled 3G mobiles, designers must also embed power-management intellectual property (IP) in their SoC designs.

Embedding power-management IP is not an easy task. To be effective, designers must tap several methods to ensure that this IP is reliable and efficient in an SoC design. These methods include design layout, transistor/resistor matching, routing and placement, and coupling noise.

Layout issues

The connection of IP blocks within a 3G cell-phone SoC is challenging, and requires applying the most rigorous design and layout expertise. The Virtual Socket Interface Alliance (VSIA) defines three areas in which a digital signal transfer can be corrupted by stray signals or noise from analog and mixed-signal blocks. These include interconnect crosstalk, substrate coupling and electromigration.

Shrinking CMOS geometries have produced high densities that can cause signal interference between neighboring interconnect wires, possibly leading to unstable SoC behavior in 3G cell-phone applications. Smaller noise margins can also result in interference between IP blocks and can make it difficult to predict signal integrity between connected logic blocks.

But by focusing on meticulous matching, routing and placement techniques, SoC designers can ensure that their 3G cell phone designs will not be crippled by inter-block interference.

Engineering know-how and expertise plays a major role in matching the transistors and the resistors SoC designs, as well as the interconnections between the different "matched" transistors and resistors. The chemical properties of the silicon substrate and the doping material will cause identically designed transistors to behave differently if placed in different locations on the SoC device. However, when two transistors are placed very close to each other, the probability they will share behavioral characteristics improves dramatically. Proximity-based matching becomes more challenging, of course, as the SoC circuit design becomes more complex and requires more transistors.

An example of matching transistors is shown (see figure). Layout A in this figure shows how, by laying out transistors (A2 - B2) and (A4 - B4) in close proximity, matching can be achieved for these two sets. However, the problem is that the set (A1 - B1) and set (A3 - B3) are not matched due to their distant location from one another. Designers can solve this problem by following the example shown in layout B, where matching is achieved for all transistor pairs.

While the matching problem can be solved for a simple design, more complex designs demand engineering knowledge and experience in power management designs. In addition to the relative location of the transistors, tools to create the dimensions as well as the location of the transistors are also essential for any power management and other analog designs.

Place and route

Routing is a second challenge to connecting the different IP blocks within a mixed-signal 3G cell-phone SoC. Design engineers follow foundry design rules when routing, and perform simulations to make sure that all of the design and routing constraints are met.

Placement of IP blocks within the SoC design also affects how the IP itself behaves and how a block might affect other neighboring IP blocks. Interference between one IP and another will affect the performance of each and as a result the behavior of the SoC. Placing electrically noisy IP away from quiet and clean IP is a good (and obvious) practice to follow. In addition, the IP designer and the layout engineer must work together and be aware of the different constraints that govern each IP block.

Reducing coupling noise

The relentless shrinking of semiconductor geometries has also caused coupling noise to become a bigger issue for designers of new and more highly integrated SoCs. One way to reduce coupling noise between P- and N-wells is to employ state-of-the-art CMOS manufacturing processes and to use features like deep N-well and shallow-trench isolation (STI) that help IC designers reduce coupling between circuit blocks.

The junction between the N and the P-wells will have a certain inductive or capacitive parasitic associated with it. This will directly impact the noise and the interference due to coupling. The deep N-well will have higher capacitance between the P and N channels, thus reducing the effects of coupling noise. Placing the N-transistors in a deep N-well of noisy IP blocks will reduce the noise to the rest of the SoC.

Another way of reducing coupling noise is to introduce an isolation layer between transistors. The STI technique can introduce this isolation layer and reduce the noise levels from coupling. This process is done at the manufacturing level where the isolation is achieved by etching and depositing.

In the past, isolation was achieved by growing a silicon-oxide layer between transistors. STI technology provides the isolation required without the added mechanical stress on the device. This presents two different ways of introducing this silicon oxide layer: STI and grown oxide. However, for both methods, the layer where the isolation is needed has to be conceived and mapped during the layout process so that the silicon substrate is masked to protect the areas where the oxide (isolation) is not needed.

For the first method, wet oxidation process is focused on the area of interest, which in turn grows a bubble of silicon dioxide that acts as an isolation layer between the transistors, as can be seen from the transmission electron microscopy (TEM) image. This method is mostly used for process of 0.35 micron or higher.

For processes lower than 0.35 micron, the transistors are placed closer to each other, presenting a challenge in creating the isolation bubble from the first method. Therefore, a channel is etched, using reactive ion etching (RIE) between the transistors. Then low-pressure vapor depression (LPCVD) process and chemical mechanical polish (CMP) are used to complete the STI process. Electrical current traveling through the substrate will encounter the isolation and will have to travel deeper into the substrate to go around it.

Even with the higher level of integration, SoCs will still have to deal with external passive components such as resistors and capacitors. When dealing with power-management blocks, the values of these external components are what determine the output voltage value and regulation. IP vendors must specify, as part of their data sheets, the values that are needed for external components or specify the relationship between the IP functionality and the value of such components. The placement of these components is also essential to the operation of certain IP blocks such as DC-DC converters and low-drop-outs (LDOs).

Mazen Allawi(mazen.allawi@ltrim.com) is the applications engineering manager at LTrim Inc. (San Jose, Calif.).

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