Power Reduction Techniques for Ultra-Low-Power Solutions

by Virage Logic Corporation

Introduction

The consumer demand for greater functionality and higher performance, but also for lower costs adds significant pressure on System-on-Chip (SoC) manufacturers. The continuing advances in process technology, and ability to design highly complex SoCs does not come without a cost. So the next generation of processes surely brings about the next generation of challenges.

With ever increasing System-on-Chip (SoC) complexity, energy consumption has become the most critical constraint for today’s integrated circuit (IC) design. Consequently, a lot of effort is spent in designing for low-power dissipation. Power consumption has become a primary constraint in design, along with performance, clock frequency and die size. Lower power can be achieved only by designing at all levels of abstraction: from architectural design to intellectual property (IP) component selection and physical implementation. Energy reduction techniques can also be applied at all levels of the system.

Designers should use components that deploy the latest developments in low-power technology. The most effective power savings can be achieved by making the right choices early on during the system and architectural level of abstraction. In addition to using power-conscious hardware design techniques, it is important to save power through careful design of the operating system and application programs.

Design Abstraction Levels

In general, power reduction can be implemented at different levels of design abstraction: system, architectural, gate, circuit and the technology level. At the system level, inactive modules may be turned off to save power. At the architectural level, parallel hardware may be used to reduce global interconnect and allow a reduction in supply voltage without degrading system throughput. Clock gating is commonly used at the gate level. A variety of design techniques can be used at the circuit level to reduce both dynamic and static power.

For a given design specification, designers have many choices to make at different levels of abstraction. Based on particular design constraints (such as power, performance, cost), the designer must select a particular algorithm, architecture and determine various parameters such as supply voltage and clock frequency. This multi-dimensional design space offers a wide range of possible trade-offs. Properties of a design are most influential at the highest levels of abstraction; therefore, the most effective design decisions derive from choosing and optimizing architectures and algorithms at those levels.

However, it becomes a challenge to predict the consequences and effectiveness of design decisions made at the higher levels of abstraction because implementation details can only be accurately modeled or estimated at the technological level. Therefore, it is important to use IP components such as embedded memories and logic libraries that offer flexibility in selecting different design and power saving techniques.

Sources of Power Dissipation

The sources of energy consumption on a CMOS chip can be classified as static and dynamic power dissipation. The dominant component of energy consumption in CMOS is dynamic power consumption caused by the actual effort of the circuit to switch. A first order approximation of the dynamic power consumption of CMOS circuitry is given by the formula:

P = C * V2 * f

where P is the power, C is the effective switch capacitance, V is the supply voltage, and f is the frequency of operation. The power dissipation arises from the charging and discharging of the circuit node capacitances found on the output of every logic gate. Every low-to-high logic transition in a digital circuit incurs a change of voltage, drawing energy from the power supply.

A designer at the technological and architectural level can try to minimize the variables in these equations to minimize the overall energy consumption. However, power minimization is often a complex process of trade-offs between speed, area, and power consumption.

Static energy consumption is caused by short circuit currents, bias, and leakage currents. During the transition on the input of a CMOS gate both p and n channel devices may conduct simultaneously, briefly establishing a short from the supply voltage to ground. While statically-biased gates are usually found in a few specialized circuits such as PLAs, their use has been dramatically reduced. Leakage current is becoming the dominant component of static energy consumption. Until recently, it was seen as a secondary order effect; however, the total amount of static power consumption doubles with every new process node.

Energy consumption in CMOS circuitry is proportional to capacitance; therefore, a technique that can be used to reduce energy consumption is to minimize the capacitance. This can be achieved at the architectural level of design as well as at the logic and physical implementation level.

Connections to external components, such as external memory, typically have much greater capacitance than connections to on-chip resources. As a result, accessing external memory can increase energy consumption. Consequently, a way to reduce capacitance is to reduce external accesses and optimize the system by using on-chip resources such as caches and registers. In addition, use of fewer external outputs and infrequent switching will result in dynamic power savings.

Routing capacitance is the main cause of the limitation in clock frequency. Circuits that are able to run faster can do so because of a lower routing capacitance. Consequently, they dissipate less power at a given clock frequency. So, energy reduction can be achieved by optimizing the clock frequency of the design, even if the resulting performance is far in excess of the requirements.

Power Reduction Techniques

One of the most effective ways of reducing power at the technological level is to reduce the supply voltage, because the power consumption drops quadratically with the supply voltage. However, lowering supply voltage results in reduction of performance; therefore, any such voltage reduction must be balanced against any performance drop. To compensate and maintain the same throughput, extra hardware can be added. This can only be successful to the point where the additional circuitry does not diminish the savings.

Modern integrated circuits requiring longer battery life are implemented with variable clock frequency and operating voltage controlled by the operating system. The variable voltage and frequency represent a trade-off between delay and power consumption. Reducing clock frequency alone doesn't necessarily reduce power, since the system must run longer to do the same work.

As voltage is reduced, the delay of the circuit increases. A common approach to power reduction is to first increase the performance of the module (by adding parallel hardware for example) and then reduce the voltage as much as possible so that the required performance is still reached. However, these techniques often translate to larger area requirements, resulting in a new trade-off between area and power.

The CMOS power consumption is proportional to the clock frequency — dynamically turning off the clock to unused logic or peripherals is an obvious way to reduce power consumption. Control can be done at the hardware level or it can be managed by the operating system of the application. For example, some systems and hardware devices have sleep or idle modes. Typically, in these modes, the clocks to most of the sections are turned off to reduce power consumption. In sleep mode, the device is not working where a wake-up event rouses the device from sleep mode. Devices may require different amounts of time to wake-up from different sleep modes.

Alternative Approaches

The alternative approach to reducing wasteful activity is applying an asynchronous design methodology. CMOS is a good technology for low-power as gates only dissipate energy when they are switching. However, many gates switch because they are connected to the clock, not because they have new inputs to process. As a result, a synchronous circuit wastes power when particular blocks of logic are not utilized. The largest gate is the clock driver, which must distribute a clock signal evenly to all parts of a circuit, and it must switch all the time to provide the timing reference even if only a small part of the chip has something useful to do.

As an alternative approach, asynchronous circuits are inherently data driven and are only active when performing useful work. Parts of an asynchronous circuit that receive less data will automatically operate at a lower average frequency. Asynchronous circuits are larger than synchronous circuits because additional logic is required for synchronization of the design.

An emerging newer approach, still in the early phase of commercial use is based on implementation of reversible logic or adiabatic logic. The fundamental premise of the reversible logic is to reduce power consumption by not erasing information. With conventional logic implementations, a bit of information is erased every time a logic operation is performed. The new approach using reversible logic operations that do not erase information can dissipate arbitrarily little heat.

Contemporary place and route systems can perform automatic transistor resizing. The optimal gate sizing is essential for achieving both performance and power consumption goals. The better drive capability of larger transistors improves the circuit performance. This also reduces the short-circuit power because of shorter rise and fall times. However, oversized transistors result in an unnecessary waste of dynamic and static power. For that reason, it is essential to use a logic library with a large number of output drive strengths.

Conclusion

Growing complexity and increasing operating clock frequencies have outpaced the scaling of process geometries and supply voltages in SoC designs, thus producing an effective rise in power dissipation by these devices and pushing heat removal and power distribution to the forefront of issues confronting the advance of microelectronics. Today system-level power management has become pervasive in the semiconductor industry and power-consumption conscious system developers are now looking for a wide range of semiconductor IP platform solutions that will eliminate the gaps between low-power and high-performance requirements.

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