Verification IP for IP verification

The intellectual-property market is still in its infancy in terms of pricing, packaging, quality and integration standards, but IP solutions for standards-based interfaces are maturing quickly. One reason for this is simply the existence of a viable market for third-party IP vendors.

Nearly all complex chip designs incorporate some form of standard interface , such as PCI Express, DDR SDRAM, USB, GigE, Advanced Switching or RapidIO. From a chip developer's perspective, these interfaces represent a complex design and verification challenge, yet they usually don't offer any significant end-product differentiation; they are simply a must-have. This makes a perfect case for outsourcing the interface design from an IP vendor, and we see this happening with great regularity in the market today. The regrettable, parallel trend is the crisis that occurs when the IP is delivered and must be integrated and verified in the context of the chip design.

Verifying IP is a more complex task than designing IP. Obviously, IP vendors must verify the correct functionality of the core. The vendor must also verify the core for compliance with the interface standard.

These tasks would be easy if interface IP were a one-size-fits-all solution. Ideally, IP vendors would provide designers with "golden IP," perfectly tailored to the application(and all future applications), preverified and silicon-proven.

See related chart Commercial verification IP solution can provide reduced risk and improved time-to-market for both IP vendors and IP customers. However, some key requirements include domain expertise, a flexible modeling approach, complete assertion libraries and compliance test suites. Source: Denali Software

But the fact is that designers always make feature and performance trade-offs that may not support the full interface specification. Even for standard interfaces like PCI Express or even DDR-SDRAM, each application requires some level of specialization in the IP core. In the most extreme case, third-party IP cores can more closely resemble service engagements, where the IP is developed exclusively for the particular application. The necessary customization of interface IP adds a new dimension of complexity to the verification task that is not present in internally developed designs.

The other element of IP verification comes into play during integration and system-level verification by the customer. The IP vendor can try to anticipate system-level interactions and verify accordingly, but the customer is ultimately responsible for the success of the chip. Even IP from the most trusted sources must undergo some additional level of functional verification at the customer site.

In addition, once the IP is integrated, the customer must verify system-level functionality and validate target performance by generating application-specific traffic. To ensure interoperability, it is also important to model other devices that might communicate through the interface in the final system.

All of these tasks, some redundant, represent a significant burden for the IP vendor and customer. IP vendors cannot afford to develop a specialized verification solution for each customer's unique design and verification environment. In addition to tailoring the verification environment to match the customized core, there are simply too many different design tools, languages and methodologies to support. Additionally, IP providers do not have the necessary visibility into the customer's design for system-level integration and verification — a lack that represents a significant new challenge to the IP customer.

These issues are common to all IP implementations and vendors, and they represent an industrywide crisis. As a result, a viable market has emerged for third-party verification IP vendors. Designers of state-of-the-art systems-on-chip are realizing the value of verification IP as the encapsulation of interface domain expertise and EDA expertise to offer significant verification productivity improvement today. Verification IP is essential for the success of the IP industry and SoC design in general.

Ideally, a commercial verification IP solution will provide reduced risk and improved time-to-market for both IP vendors and IP customers. While the market is quickly refining the requirements, we have found that commercially successful verification IP solutions must include the following key elements:

• Domain expertise and participation in the development of interface standards.
• A flexible modeling approach to encapsulate domain expertise and enable modeling of vendor-specific subsets of the interface standard (includes BFM).
• Complete assertion libraries (also known as checkers or monitors) for verifying compliance with the interface specification.
• Compliance test suites to exercise the design with compliant and noncompliant traffic.
• Application-specific traffic generation to support system-level verification.
• A coverage engine to identify corner-cases and test completeness.
• Portability across testbench environments and verification languages to enable quality through a single, reusable solution for an industrywide user base.
• Easy integration to other tools for coverage, transaction analysis and debug.

As the IP market develops to support SoC design, a parallel market for verification IP is accelerating. Verification IP is essential for the success of the IP industry and SoC design in general. Commercial verification IP is being leveraged successfully in IP development and deployment, as well as system integration and verification.

Successful verification IP companies encapsulate EDA expertise with an expert-level understanding of interface standards to address these key requirements in a comprehensive verification IP solution.

David Lin (david@denali.com) is a vice president at Denali Software (Palo Alto, Calif.).