Advantages of FPGA design methodologies

As FPGA devices progressed both in terms of resources and performance, the latest FPGAs have come to provide "platform" solutions that are easily customizable for system connectivity, DSP, and/or data processing applications. As platform solutions are becoming more and more important, leading FPGA vendors are coming up with easy-to-use design development tools.

These platform building tools accelerate time-to-market by automating the system definition and integration phases of system on programmable chip (SOPC) development. The tools not only improve design productivity, but also reduce the cost of buying these tools from 3rd party EDA vendors. Using such tools, system designers can define a complete system, from hardware to software, within one tool and in a fraction of the time of traditional system-on-a-chip (SOC) design.

DSP design

DSP system design in programmable logic devices requires both high-level algorithm and hardware description language (HDL) development tools. Major FPGA vendors offer DSP builder tools that combine the algorithm development, simulation, and verification capabilities of Matlab and Simulink with synthesis, simulation, and place and route.

These tools shorten DSP design cycles by helping designers create the hardware representation of a DSP design in an algorithm-friendly development environment. The existing Matlab functions and Simulink blocks can be combined with FPGA vendor blocks and vendor intellectual property (IP) functions to link system-level design and implementation with DSP algorithm development. This allows system, algorithm, and hardware designers to share a common development platform.

Designers can create a hardware implementation of a system modeled in Simulink in sampled time. DSP tools contain bit and cycle-accurate Simulink blocks, which cover basic operations such as arithmetic or storage functions. With the availability of such tools, designers are able to generate and refine algorithmic designs in a fraction of the time that it took to hand code RTL.

IP integration

With the availability of multi-million gate FPGAs, to become significantly productive, the designer has to leverage the use of IP as much as possible. Integration of a third party IP is not that easy to perform, as one has to verify the IP to the targeted technology and then make sure that the IP meets the area and performance specification.

But with FPGAs, the vendors themselves take the trouble of verifying the third party and in-house developed IP for area and performance. The biggest advantage of platform based design is that it supports integration of proprietary logic along with third party IP.

The challenge for any system-on-a-chip FPGA is to verify the functionality of the complete system that includes processor cores, third party IP and proprietary logic. To perform this type of verification, along with a high speed simulator, verification engineers also need a complete suite of verification tools. To support system verification, the FPGA design methodology supports formal verification and static timing analysis.

Tool support

FPGA design flows support the use of third party EDA tools to perform design flow tasks such as static timing analysis, formal verification, and RTL and gate level simulation.

Traditionally, FPGA design and PCB design has been done separately by different design teams using multiple EDA tools and processes. This can create board level connectivity and timing closure challenges, which can impact both performance and time-to-market for designers. New EDA tools bring together PCB solutions and FPGA vendor design tools, helping enable a smooth integration of FPGAs on PCBs.

Transition to structured ASICs

When the demand for the FPGA parts increases, FPGA vendors provide a comprehensive alternative to ASICs called structured ASICs that offer a complete solution from prototype to high-volume production, and maintain the powerful features and high-performance architecture of their equivalent FPGAs with the programmability removed. Structured ASIC solutions not only provide performance improvement, but also result in significant cost reduction.

With the advent of new technologies in the field of FPGAs, design houses are provided with an option other than ASICs. With the mask costs approaching a one million dollar price tag, and NRE costs in the neighborhood of another million dollars, it is very difficult to justify an ASIC for a low unit volume. FPGAs, on the other hand, have improved their capacity to build systems on a chip with more than million ASIC equivalent gates and a few megabits of on chip RAM. For high volumes, a structured ASIC solution combines the cost advantage of ASICs with a low risk solution of an FPGA.

Shekar Chandrashekar is member of technical staff for software applications at Altera Corp.