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Today's DSP Design Challenge - Power Efficiency
By Hans Roeven and Norm Kelly
The most important design goal in new processor developments is power efficiency. With silicon implementation technologies scaling rapidly to 90nm and beyond, power consumption is a primary issue holding back SoC designers from integrating more functions on a single chip. In order to attack this problem when designing a new DSP, the best approach is a holistic one. This article will discuss how Synopsys and Phillips met the power efficiency challenge.
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The most important design goal in new processor developments is power efficiency. With silicon implementation technologies scaling rapidly to 90nm and beyond, power consumption is a primary issue holding back SoC designers from integrating more functions on a single chip. In order to attack this problem when designing a new DSP, the best approach is a holistic one. This article will discuss how Synopsys and Phillips met the power efficiency challenge.
Click here to read more
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