English
TLM Peripheral Modeling for Platform-Driven ESL Design Using the SystemC Modeling Library
by Tim Kogel, CoWare Inc., Solution Specialist
Abstract
This article provides an overview of a SystemC-based Transaction Level Modeling (TLM) methodology for the rapid creation of SoC platform models. First a brief overview of the ESL design tasks and the corresponding modeling requirements is given. The main topic is a methodology for the efficient creation of transaction-level peripheral models. Those are usually specific for a particular SoC platform and have to be created by the ESL user.
Click here to access this paper (PDF file)
Related Articles
- Step Up to C for Embedded R&D
- Methodology for Rapid Development of Loosely Timed and Approximately Timed TLM Peripherals
- SystemC: Key modeling concepts besides TLM to boost your simulation performance
- Design & Verify Virtual Platform with reusable TLM 2.0
- Using IP-XACT Metadata for a TLM Modeling Flow
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow
|
E-mail This Article | 
|
|
Printer-Friendly Page |