Platform ASICs stake the middle ground

FPGA and ASIC vendors have traditionally battled over low-complexity designs. In the past couple of years, however, a new contender has entered the fray called the platform ASIC. This newcomer more closely resembles its brother, the higher-complexity cell-based ASIC, in terms of features, performance and unit cost. Yet, it has added benefits, namely, intellectual-property (IP) reuse, ease of design and metal mask configurability.

The platform ASIC is proving to be a viable solution for reducing the costs of systems containing one or more complex FPGAs and where lifetime unit volumes are in the range of 5,000 and above. In addition, hardware and chip designers who can't afford the up-front costs of cell-based ASICs have migrated to platform ASICs, which still meet their system requirements. For these designers, the relatively low-complexity FPGA never was-and never will be-an option.

LSI Logic's RapidChip Platform is an example of this approach, and has been adopted by some large OEMs such as Seagate as well as startups like Whiterock, Spidcom and others in all geographies. They have been able to use IP ranging from embedded processors to highly complex, standards-compliant serializer/deserializers at up to 4.25 Gbits/second. On average, the total time from design start to silicon in hand is six months, though one customer received silicon three months after initial discussions began. These designs are well in excess of 1 million real gates in complexity, not including the IP. This is an area in which FPGA products cannot operate.

FPGAs do have an important role to play, however. They are quickly programmed or reprogrammed to deploy to market and keep engineering costs to a minimum. In fact, they have won the battle over traditional gate arrays. However, the ability of the FPGA to move up the complexity continuum and seriously challenge platform ASICs and cell-based ASICs is limited by physics and technology barriers that are increasing with each technology node. The limits manifest themselves most notably in the form of power and performance.

During his keynote speech at this year's Design Automation Conference in San Diego, Intel CTO Pat Gelsinger highlighted power as one of the key issues facing the industry. FPGAs, with their regular programmable-logic block and global interconnect structure, suffer more from this phenomenon than do cell-based or platform ASICs because FPGA architectures are transistor-hungry. This is the trade-off for their value-add: instant programmability. A large number of transistors are consumed in the programming overhead on top of the transistors used for the logic itself, and all the transistors are powered up all the time.

This effect is exacerbated at 90 nanometers due to the low threshold voltages (VT) required to meet performance needs. The compounding effect is that FPGAs cannot afford to trade in performance due to the choking effect of the interconnect. Because of this effect, we see that FPGA structures in the newest 90-nm technology are already starting to draw as much static power, with no clock applied, as dynamic power on a clocked ASIC.

Comparably, cell-based ASICs take considerably less power than FPGAs, both in dynamic and static power. Interestingly, platform ASICs track closely to cell-based ASIC power usage and offer a slight improvement when comparing power. This is due to the transistor within the R-cell logic fabric of the RapidChip Platform ASIC being slightly smaller than its cell-based equivalent, thus slightly reducing effects of dynamic and static current. In addition, the ASIC design flow and methodology provide more degrees of freedom to reduce power consumption.

Threshold voltage optimization, where slower (less leaky) transistors are swapped into the layout during timing closure to reduce power, is already becoming the norm in 130- and 90-nm ASIC flows. The use of voltage islands, where different voltages are created for specific blocks of logic on the same die, is also becoming widespread. Power-down, where the power mesh either receives a reduced voltage or is even reduced to zero in a sleep mode, is also being debated, but this currently lacks EDA automation. All these technology advances are directly applicable to ASIC designs but are impossible to use within an FPGA structure. Which gates would you choose to make high VT and, therefore, low performance in reconfigurable logic? Which blocks should you make permanently lower voltage or with a sleep mode?

Nothing is free
Recently, there has been much debate about other techniques aimed at reducing power, notably, the use of thicker gate oxides. Use of thicker gate oxides does reduce leakage current, but nothing is free. The trade-off is significantly reduced transistor drive currents and, therefore, chip-level performance. Because they are interconnect-dominated, FPGA architectures cannot afford any reduction in transistor drive, especially in the newer technology nodes where as much as 90 percent of the signal delay can be apportioned to interconnect.

While we see power and performance at 90 nm and going forward as a definite industry issue, some silicon structures (FPGAs) will disproportionately suffer from these effects more than others (cell-based and platform ASICs). The future appears to be bright for FPGAs as a prototype verification vehicle. Controlling power (as well as performance and die size) may be too big a hurdle for FPGAs to be used in volume production in many applications.

Ronnie Vasishta is vice president of technology marketing at LSI Logic Corp. (Milpitas, Calif.).

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