Integrating High Speed Serial Transceivers into an FPGA

The acceptance of serial standards and protocols like PCI Express, Serial Rapid I/O and SerialLite will increase the use of high-speed serial transceivers with clock and data recovery (CDR). These transceivers, once offered in quad or octal application-specific standard products (ASSPs), are now integrated in high-end FPGAs. The benefits of less board space, increased flexibility and the absence of interfacing issues with two-chip solutions make FPGAs with embedded transceivers an attractive solution to board designers.

Pulling transceivers into FPGAs shifts interfacing issues from board designers to chip designers. This is particularly the case when incorporating 16 x 3.125-Gbit/s high-speed transceivers into an FPGA. The integration challenges fall into four categories: floor planning, design methodologies, layout and packaging.

Floor planning Creating a floor plan to accommodate two derivatives of an FPGA — one without transceivers and the other with transceivers — was complex. We designed the device without transceivers first. When it came time to design the device with transceivers, we reused 80 percent of the floor plan from the first device. We stripped off low-voltage differential-signaling I/O blocks on the right side of the transceiverless device's floor plan and replaced them with transceiver blocks.

To minimize risk, we validated the transceiver design first with a test chip that was fully characterized. Once improvements were incorporated into the transceiver design, we instantiated 16 transceiver blocks to create the device with transceivers.

Another challenge was to optimize signal integrity for high-speed transceiver paths on the die. The shortest path is optimum. Transceiver I/Os were vertically connected to bump arrays on the die surface, avoiding several metal-interconnect layers in between. The metal layers in the transceiver block had to be manually routed to clear a way for the vertical connections. The FPGA was designed in a Taiwan Semiconductor Manufacturing Co. Ltd. 0.13-micron process.

Design and Simulation

The transceiver required a design methodology that was different from the FPGA fabric, which created an integration challenge. The transceiver was composed of mixed-signal blocks that included a phase-locked loop (PLL), CDR, pre-emphasis, equalizer, rate matcher, word aligner, an 8-byte/10-byte encoder/decoder, pattern detector and state machine blocks.

Designing the transceiver and FPGA required a novel mixed-signal simulation environment. First, individual analog blocks were designed and simulated using standard schematic-based Spice netlists. Things get tricky when simulating multiple analog blocks together, however: Simulation times can get very long for such system-level tests as wake-up from reset to CDR lock to acquiring byte align. To overcome this obstacle, hardware description language (HDL) representations were created for all the analog blocks.

When incorporating 16 x 3.125-Gbit/s high-speed transceivers into an FPGA integration challenges fall into four categories: floor-planning; design methodologies, layout; and packaging. Source: Altera Corp.

On a case-by-case basis for each system-level test, specific analog blocks deemed noncritical would be replaced with HDL models while others might still be Spice netlists. These mixed HDL/Spice analog block netlists were combined with HDL models (or in some cases gate-level netlists with back-annotated timing) for the digital blocks, thereby creating a realistic system-level simulation. The above mixed-signal simulation methodology also reused Verilog testbenches used to simulate the RTL-based digital logic.

FPGAs face another unique verification challenge. The functionality of the millions of computational RAMs as interpreted by the FPGA design tool — such as Quartus — needs to be verified. A common set of input vectors and CRAM settings were applied to both the design tool's internal database and IC design's mixed Verilog/schematics database. The results from both simulations had to match.

Layout integration

Layout presented two challenges: electrical isolation of the transceiver block from the rest of the FPGA and different layout rules for the FPGA and transceiver.

Because of stringent transceiver jitter generation and tolerance specifications, the transceiver block needs to be isolated from the rest of the FPGA. Transceiver blocks are surrounded by a deep N-well ring to keep noise from the FPGA fabric from coupling into sensitive circuits like the PLL and CDR. Power and ground for each transceiver block is unique and isolated from the others. Each is connected to its own ground and power balls.

Although the FPGA and transceiver were on the same die, the design rules for each were slightly different. Full-chip layout verification for the transceiver and FPGA required separate design rule checking (DRC) and layout vs. schematic (LVS). A ring around the transceivers was defined as an interconnect zone and only metal-routed signals crossed over this ring. Once we verified the transceiver and FPGA were DRC-clean, a partial design rule check over the interconnect zone was applied in order to merge them into a single database.

Package selection
Selecting a package that supports multi-gigabit speeds is critical. A flip-chip fine-line ball grid array package that uses multilayer FR4 material as a substrate met the criteria. The high-speed I/O paths were prioritized and kept as short as possible. In addition, we controlled the trace impedance and minimized the number of vias traversed by a high-speed signal. Over 200 critical path simulations from die bump to package ball ensured optimal signal integrity. Advanced modeling tools, HFSS and Ansoft were used to extract Spice models for traces and vias. Finally, special attention was devoted to the power and ground planes and path to minimize crosstalk and noise.

The integration of transceivers into FPGAs, ASSPs and ASICs will not stop at 3.125 Gbits/s. Next-generation FPGAs will have higher-speed transceivers running at 6.5 Gbits/s to 10 Gbits/s. The integration challenges will only increase with faster data rates.

Ramanand Venkata is a member of the technical staff and Joel Martinez is product-marketing manager for Altera Corp. (San Jose, Calif.).