Reuse of Analog Mixed Signal IP for SoC Design: Progress Report (Cadence Design Systems)

Even when designers work with a well-defined standard like a PCI Express serializer-deserializer (serdes), for example, significant modifications may be required, depending on such variables as whether the end user wants a wirebond or flip-chip package, the desired I/O pitches, the number of metal layers in the technology process or whether the user wants to use the "low-voltage" vs. "generic" flavor of that process.

Analog performance sensitivity to all these variables precludes a "one-size-fits-all" solution. Nevertheless, analog designers and tool companies have made significant progress in a couple of key areas. The first is in the development of standards around AMS interfaces, along with the concept of "base designs" that can be efficiently retargeted. The second is in the development of new software tools for migrating analog circuits across similar process technologies.

Why AMS interface standards?
With the advent of standard high-speed serial bus interfaces over the past several years, and using careful design techniques, one can build a base serdes with a set of variants that can be used multiple times off the shelf. By partitioning the design into reusable sub-blocks that can be configured in multiple ways, one gets a set of serdes macros that meet the needs of most standard applications. Custom configurations are handled by reusing the same sub-blocks with custom placement and routing. These reusable sub-blocks can also be ported to similar process nodes to provide the same capability in other processes.

To develop these reusable serdes blocks, the design team had to make many specification and design trade-offs that involved balancing flexibility, cost of reuse and the cores' overall marketability. The first major trade-off was in determining how many serdes standards to cover with a single reusable core. This decision impacted the basic architecture, size, power and the amount of programmability built into each of the blocks. Our particular design addressed standards ranging from Gigabit Ethernet, Sonet, XAUI, Fibre Channel, Infiniband and Serial Rapid IO.

The choice of process technology also presented critical trade-offs. We wanted to select a process that was efficient to work with, had sufficient performance and robustness and would appeal to a broad base of customers and applications. To remain compatible with standard digital SoC designs, we chose the Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) 130-nanometer generic logic process without any special process options. The team also believed that this choice represented the best starting point for future porting.

The key technical challenge was maintaining competitive power and area while still meeting the various standards. The variable number of lanes each standard required led to a "rack and stack" architecture with building blocks that permitted from one to 16 lane configurations. This proved to be a good choice, as it simplified reuse and was a major selling point for the core.

The biggest impact on the design's power consumption was the requirement to handle both dc- and ac-coupled standards with a variety of common-mode and signal swing voltages. To implement this, the design used both 3.3-volt and 1.2-V supplies. This tied the design to only one I/O voltage option in the process and increased the power dissipation in the high-swing 3.3-V driver. Overall, these choices may have reduced the marketability of the core for certain applications, in exchange for greater flexibility and lower reuse cost.

Another technical challenge was in making the reusable core robust. The design team managed to design to the worst-case three-sigma corners of the process. The result was a design that performed robustly over process, temperature and voltage variations and yielded extremely well. This proved to be a strong selling point for the design, although in certain applications the benefit was offset by the larger design layout required to meet worst-case conditions.

AMS porting
Automated porting of AMS IP between processes to enable reuse has been an elusive goal. Recent strides in developing porting software are helping considerably, however, in the migration of designs between similar process technologies. In the case of the serdes design just described, three approaches were evaluated.

All three began with the use of a schematic re-referencer. The re-referencer tool permits the designer to do a direct schematic map to the new process components and to scale any devices based upon parameter differences between the old and new process targets. This step worked extremely well.

Porting the physical layout proved more challenging, however. In the first approach a migration tool, Virtuoso Layout Migrate, was used to port the original layout to the new process. The second approach used a constraint-driven layout tool, Virtuoso Neocell, that creates a totally new layout using designer-entered constraints. The third approach consisted of performing the physical layout from scratch using the semiautomated design tools that are part of a standard Virtuoso design flow.

The first two approaches showed good results at the block level but required the team to partition larger macros into blocks. The major drawback of these approaches was the length of time required for tool setup before each port, which resulted in an overall porting time/effort equivalent to the standard design flow used in the third approach. For someone who has a significant number of similar blocks to port between two specific processes, this would not be an issue. Once improvements are made to reduce tool setup time and develop a more comprehensive flow that ties the tools together within a framework with standard testbenches and a circuit optimizer, automated porting processes will become a mainstream path for AMS designers. Cadence is actively working to bring these pieces together in the near future within the Virtuoso Custom Design Platform.

In addition to leveraging reusable standard-based designs and porting tools, there are other trends that will aid analog IP reuse in the future. One of the most important is the convergence of process technologies at lower geometry nodes. For example, TSMC and IBM Corp. are propagating their technologies to IDMs and partners, and smaller players are developing processes very similar to those of the major pure-play foundries. With fewer process variants, it will be possible to service more customers and applications with fewer IP variants. This will lead to more AMS blocks that are truly reusable off the shelf. Moreover, convergence will also help to alleviate the SoC developer's greatest fears: schedule and risk.

Tim Henricks (henricks@cadence.com) is vice president of Engineering Services at Cadence Design Systems Inc. (San Jose, Calif.).

See related chart Developing re-usable serdes blocks involves many specification and design tradeoffs to balance flexibility, cost of reuse and the cores' overall marketability. Source: Cadence Design Systems Inc.