D&R Industry Articles

Articles for the Week of February 17, 2025

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Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices

In this blog post, we shall explore the methodology of 3D reconstruction on the multi-view object scenes, used for volumetric object dimensioning in autonomous robots. We shall also detail the steps of capturing data streams, generating object point clouds, reconstructing 3D point clouds through local and global registration algorithms, and calculating object dimensions in 3D. The results will be presented at the end.

• Why RISC-V is a viable option for safety-critical applications

Articles for the Week of February 10, 2025

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Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World

Quantum computing advances are exciting, but they’re also a looming threat to securing ICs, driving the need for Post-Quantum Cryptography (PQC). Learn about PQC, how it’s being implemented, and the legislation involved.

• What is JESD204B? Quick summary of the standard

Articles for the Week of February 3, 2025

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Analysis and Summary on Clock Generator Circuits and PLL Design

The demand for analog and mixed-signal-based integrated circuits (ICs) has surged due to the increasing reliance on electronic-based applications across industries. As the world transitions to more advanced technologies, low-noise, low-power systems have become highly competitive in achieving optimal design performance. Among the most critical components are clock generator circuits, which require low phase noise and low jitter for high-precision operation.

• Understanding why power management IP is so important
• Hardware-Assisted Verification: The Real Story Behind Capacity

Articles for the Week of January 27, 2025

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Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design

As the semiconductor industry pushes the boundaries of innovation, modern system-on-chip (SoC) designs are growing exponentially in size and complexity. With hundreds of IP blocks and thousands of interconnects to manage, the challenges of maintaining performance, maximizing efficiencies, and meeting time-to-market demands are more significant than ever.

• SoC design: What's next for NoCs?
• How to Save Time and Improve Communication Between Semiconductor Design and Verification Engineers

Articles for the Week of January 20, 2025

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Accelerating RISC-V development with Tessent UltraSight-V

Siemens’ longstanding and deep engagement with the RISC-V community dates back to the foundation’s early days. Involved initially as the independent company UltraSoC, now as Siemens EDA, Siemens has played a significant role in shaping the RISC-V ecosystem, mainly through technical contributions and ongoing participation in relevant working groups.

• Synopsys Foundation IP Enabling Low-Power AI Processors
• Automotive Ethernet Security Using MACsec

Articles for the Week of January 6, 2025

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Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology

This white paper explores the integration of advanced PVT sensors into DVFS frameworks to overcome these limitations. Building on research innovations in energy-efficient computing, the paper demonstrates how Innosilicon’s PVT sensor provides a reliable and scalable solution to address process variability, voltage scaling, and thermal management.

• What is JESD204C? A quick glance at the standard
• Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology

Articles for the Week of December 16, 2024

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A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)

TMR is not a new idea in the world of ASIC design. It was published as far back as 1962 in the IBM Journal of Research and Development. However, it has become an essential design solution for ASIC chips sent into space, a vast environment filled with radiation.

• Quantum Readiness Considerations for Suppliers and Manufacturers

Articles for the Week of December 2, 2024

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The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification

Building on the success of achieving PSA Certified™ Level 2 Ready through the integration of PUFcc with Arm’s CPU, Corstone platform, and TF-M, PUFsecurity and Arm move forward to the next level and successfully attain SESIP and PSA Certified™ Level 3 RoT Component certification for PUFsecurity’s Crypto Coprocessor IP, PUFcc.

• Early Interactive Short Isolation for Faster SoC Verification
• Advanced Packaging and Chiplets Can Be for Everyone

Articles for the Week of November 25, 2024

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Timing Optimization Technique Using Useful Skew in 5nm Technology Node

The relentless march towards shrinking technology nodes has ushered in a new era of intricate semiconductor designs characterized by a proliferation of transistors. This intensifying complexity brings with it heightened criticality in various aspects of chip design and manufacturing. As each day dawns, innovative techniques and methodologies emerge to tackle these burgeoning challenges and fortify the compatibility of cutting-edge electronic devices.