D&R Industry Articles

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A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)

TMR is not a new idea in the world of ASIC design. It was published as far back as 1962 in the IBM Journal of Research and Development. However, it has become an essential design solution for ASIC chips sent into space, a vast environment filled with radiation.

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The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification

Building on the success of achieving PSA Certified™ Level 2 Ready through the integration of PUFcc with Arm’s CPU, Corstone platform, and TF-M, PUFsecurity and Arm move forward to the next level and successfully attain SESIP and PSA Certified™ Level 3 RoT Component certification for PUFsecurity’s Crypto Coprocessor IP, PUFcc.

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Timing Optimization Technique Using Useful Skew in 5nm Technology Node

The relentless march towards shrinking technology nodes has ushered in a new era of intricate semiconductor designs characterized by a proliferation of transistors. This intensifying complexity brings with it heightened criticality in various aspects of chip design and manufacturing. As each day dawns, innovative techniques and methodologies emerge to tackle these burgeoning challenges and fortify the compatibility of cutting-edge electronic devices.

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Streamlining SoC Design with IDS-Integrate™

System-on-chip (SoC) designers face significant challenges when integrating thousands of IP blocks from various vendors, often presented in different formats. The manual stitching and debugging of these components can result in quality issues, extended time-to-market (TTM), and complex integration hurdles.

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CANsec: Security for the Third Generation of the CAN Bus

CANsec is a resource-efficient solution for securing the CAN bus against the most common cyber security threats on software-defined vehicles. Here we show that the encryption and authentication of CAN XL frames are possible without latencies or loss of bandwidth.

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Accelerating SoC Evolution With NoC Innovations Using NoC Tiling for AI and Machine Learning

A new trend is emerging in the design of high-end, multi-billion-transistor system-on-chip (SoC) devices. Referred to as “NoC tiling,” this evolutionary approach uses proven, robust network-on-chip (NoC) technology to facilitate scaling, condense design time, speed testing, and reduce risk.

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A new era for embedded memory

While flash memory is still the most popular non- volatile memory (NVM), several applications are beginning to adopt other types of embedded NVM technology, both because embedded flash can’t feasibly scale beyond 28nm and because of cost, power, and performance advantages.

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Casting a wide safety net through post processing Checking

In this paper, we explain how we adopted the post processing method to make sure we check for signatures that are expected are present in the log files. This acted as a safety net when engineers made inadvertent mistakes and introduced issues in the code base.