D&R Industry Articles (October 2002)

Articles for the Week of October 28, 2002

• Applications drive trend to serial I/O
• SerDes power minimization allows SoC solutions
• Building a verification strategy 'blueprint'
• 3-D bin packing algorithm proposed for SoC testing
• Flood of serial entrants confounds designers
• Robust designs cut vendor hype
• Too many specs confuse server design
• Architecture backs up all local I/Os
• Compatibility issue slows PCI Express
• Serial schemes eyed for disk storage
• Backplanes: tough interconnect choices
• Advanced switching boosts PCI Express
• How HyperTransport and PCI Express complement each other
• Making the best interconnect choice: weighing the pros and cons
• Rapid IO fits interconnect requirements for embedded systems
• Common physical layer issues underlie new I/O standards

Articles for the Week of October 21, 2002

• Assertion-based verification streamlines design outsourcing
• Building a Verification Pyramid

Articles for the Week of October 14, 2002

• Assertions aid design-for-verification strategy
• SoCs no panacea for comms infrastructure
• Benefits, risks in 90-nm SoC solutions
• Smart partitioning eyes 3G basestation
• IC suppliers ramp system-level design
• Amplifier linearization promotes efficiency in multi-carrier WCDMA basestation
• Tailoring is critical to successful RF analog CMOS chips
• Making interrupt design firmware friendly
• Embedded processors, cores target broad app range
• New approach moves logic BIST into mainstream

Articles for the Week of October 7, 2002

• Commentary: Canadian universities tackle SoCs
• Proof engines are vital to SoC flows
• LVDS ups A/D converter data rates
• Data interface key to future apps

Articles for the Week of September 30, 2002

• Open-source cores provide new paths to SoCs
• DFT for SoC : The Economic Myths